SLASFD4A August   2024  – July 2026 TAS2020

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Device Functional Modes
      1. 6.3.1 Operational Modes
        1. 6.3.1.1 Hardware Shutdown
        2. 6.3.1.2 Hardware Config Modes
        3. 6.3.1.3 Software Power Modes Control and Software Reset
        4. 6.3.1.4 Efficiency and power saving modes
          1. 6.3.1.4.1 Noise Gate
          2. 6.3.1.4.2 Music Efficiency Mode
      2. 6.3.2 Faults and Status
        1. 6.3.2.1 Interrupt generation and clearing
    4. 6.4 Feature Description
      1. 6.4.1 PurePath™ Console 3 Software
      2. 6.4.2 Playback Signal Path
        1. 6.4.2.1 Digital Volume Control and Amplifier Output Level
        2. 6.4.2.2 High Pass Filter
        3. 6.4.2.3 Class-D Amplifier
        4. 6.4.2.4 Supply Tracking Limiters with Brown Out Prevention
          1. 6.4.2.4.1 Voltage Limiter and Clipping protection
        5. 6.4.2.5 Tone Generator
      3. 6.4.3 Digital Audio Serial Interface
        1. 6.4.3.1 Digital Loopback
      4. 6.4.4 Thermal Protection
      5. 6.4.5 Clocks and PLL
        1. 6.4.5.1 Auto clock based wakeup and clock errors
      6. 6.4.6 Digital IO pins
    5. 6.5 Programming
      1. 6.5.1 I2C Control Interface
      2. 6.5.2 I2C Address Selection
      3. 6.5.3 General I2C Operation
      4. 6.5.4 I2C Single-Byte and Multiple-Byte Transfers
      5. 6.5.5 I2C Single-Byte Write
      6. 6.5.6 I2C Multiple-Byte Write
      7. 6.5.7 I2C Single-Byte Read
      8. 6.5.8 I2C Multiple-Byte Read
  8. 7 Register Maps
    1. 7.1 PAGE 0 Registers
    2. 7.2 PAGE 1 Registers
    3. 7.3 PAGE 2 Registers
    4. 7.4 PAGE 4 Registers
    5. 7.5 PAGE 5 Registers
    6. 7.6 PAGE 6 Registers
    7. 7.7 PAGE 7 Registers
    8. 7.8 PAGE 8 Registers
    9. 7.9 BOOK100 PAGE9 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Mono/Stereo Configuration
        2. 8.2.2.2 EMI Passive Devices
        3. 8.2.2.3 Miscellaneous Passive Devices
      3. 8.2.3 Application Performance Plots
    3. 8.3 What to Do and What Not to Do
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

6.4.5 Clocks and PLL

In TDM/I2S Mode, the device operates from SBCLK. Table 6-23 below shows the valid SBCLK frequencies for each sample rate and SBCLK to FSYNC ratio. For 44.1kHz based clocking, the same table is applicable with the associated ratio change between 48ksps to 44.1ksps.

While the sampling rate of 192kHz is supported, data is internally down-sampled to 96kHz. Therefore audio content greater than 40kHz must not be applied to prevent aliasing. This additionally affects all processing blocks like BOP and limiter which must use 96kHz fs when accepting 192kHz audio.

If the sample rate is properly configured via the SAMPLE_RATE_CFG bits, no additional configuration is required as long as the SBCLK to FSYNC ratio is valid. The device automatically detects the input PCM FSYNC and BCLK frequency and auto configures itself to playback audio signal. The detected clock rates can be read using the read only registers FS_RATIO_DETECTED and FS_RATE_DETECTED. The device detects improper SBCLK frequencies and SBCLK to FSYNC ratios and volume ramp down the playback path to minimize audible artifacts.

Table 6-23 Supported SBCLK Frequencies (MHz) (48kHz based sample rates)
Sample Rate (kHz)SBCLK to FSYNC Ratio
162432486496128192256384512125250500
16kHzNA0.3840.5120.7681.0241.5362.0483.0724.0966.1448.192248
24kHz0.3840.5760.7681.1521.5362.3043.0724.6086.1449.21612.2883612
32kHz0.5120.7681.0241.5362.0483.0724.0966.1448.19212.28816.3844816
48kHz0.7681.1521.5362.3043.0724.6086.1449.21612.28818.43224.57661224
96kHz1.5362.3043.0724.6086.1449.21612.28818.43224.576NANA1224NA
192kHz3.0274.6086.1449.21612.28818.43224.576NANANANA24NANA