SLASFD9 April   2025 TAC5301-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Electrical Characteristics
    7. 5.7  Timing Requirements: I2C Interface
    8. 5.8  Switching Characteristics: I2C Interface
    9. 5.9  Timing Requirements: TDM, I2S or LJ Interface
    10. 5.10 Switching Characteristics: TDM, I2S or LJ Interface
    11. 5.11 Timing Diagrams
    12. 5.12 Typical Charactaristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Serial Interfaces
        1. 6.3.1.1 Control Serial Interfaces
        2. 6.3.1.2 Audio Serial Interfaces
          1. 6.3.1.2.1 Time Division Multiplexed Audio (TDM) Interface
          2. 6.3.1.2.2 Inter IC Sound (I2S) Interface
          3. 6.3.1.2.3 Left-Justified (LJ) Interface
        3. 6.3.1.3 Using Multiple Devices With Shared Buses
      2. 6.3.2 Phase-Locked Loop (PLL) and Clock Generation
      3. 6.3.3 Input Channel Configuration
      4. 6.3.4 Output Channel Configurations
      5. 6.3.5 Reference Voltage
      6. 6.3.6 Microphone Bias
      7. 6.3.7 Signal-Chain Processing
        1. 6.3.7.1 ADC Signal-Chain
          1. 6.3.7.1.1  Programmable Channel Gain and Digital Volume Control
          2. 6.3.7.1.2  Programmable Channel Gain Calibration
          3. 6.3.7.1.3  Programmable Channel Phase Calibration
          4. 6.3.7.1.4  Programmable Digital High-Pass Filter
          5. 6.3.7.1.5  Programmable Digital Biquad Filters
          6. 6.3.7.1.6  Programmable Channel Summer and Digital Mixer
          7. 6.3.7.1.7  Configurable Digital Decimation Filters
            1. 6.3.7.1.7.1 Linear-phase filters
              1. 6.3.7.1.7.1.1 Sampling Rate: 8kHz or 7.35kHz
              2. 6.3.7.1.7.1.2 Sampling Rate: 16kHz or 14.7kHz
              3. 6.3.7.1.7.1.3 Sampling Rate: 24kHz or 22.05kHz
              4. 6.3.7.1.7.1.4 Sampling Rate: 32kHz or 29.4kHz
              5. 6.3.7.1.7.1.5 Sampling Rate: 48kHz or 44.1kHz
              6. 6.3.7.1.7.1.6 Sampling Rate: 96kHz or 88.2kHz
              7. 6.3.7.1.7.1.7 Sampling Rate: 192kHz or 176.4kHz
            2. 6.3.7.1.7.2 Low-latency Filters
              1. 6.3.7.1.7.2.1 Sampling Rate: 24kHz or 22.05kHz
              2. 6.3.7.1.7.2.2 Sampling Rate: 32kHz or 29.4kHz
              3. 6.3.7.1.7.2.3 Sampling Rate: 48kHz or 44.1kHz
              4. 6.3.7.1.7.2.4 Sampling Rate: 96kHz or 88.2kHz
              5. 6.3.7.1.7.2.5 Sampling Rate: 192kHz or 176.4kHz
            3. 6.3.7.1.7.3 Ultra-Low-Latency Filters
              1. 6.3.7.1.7.3.1 Sampling Rate: 24kHz or 22.05kHz
              2. 6.3.7.1.7.3.2 Sampling Rate: 32kHz or 29.4kHz
              3. 6.3.7.1.7.3.3 Sampling Rate: 48kHz or 44.1kHz
              4. 6.3.7.1.7.3.4 Sampling Rate: 96kHz or 88.2kHz
              5. 6.3.7.1.7.3.5 Sampling Rate: 192kHz or 176.4kHz
          8. 6.3.7.1.8  Automatic Gain Controller (AGC)
          9. 6.3.7.1.9  Voice Activity Detection (VAD)
          10. 6.3.7.1.10 Ultrasonic Activity Detection (UAD)
        2. 6.3.7.2 DAC Signal-Chain
          1. 6.3.7.2.1 Programmable Channel Gain and Digital Volume Control
          2. 6.3.7.2.2 Programmable Channel Gain Calibration
          3. 6.3.7.2.3 Programmable Digital High-Pass Filter
          4. 6.3.7.2.4 Programmable Digital Biquad Filters
          5. 6.3.7.2.5 Configurable Digital Interpolation Filters
            1. 6.3.7.2.5.1 Linear-phase filters
              1. 6.3.7.2.5.1.1 Sampling Rate: 8kHz or 7.35kHz
              2. 6.3.7.2.5.1.2 Sampling Rate: 16kHz or 14.7kHz
              3. 6.3.7.2.5.1.3 Sampling Rate: 24kHz or 22.05kHz
              4. 6.3.7.2.5.1.4 Sampling Rate: 32kHz or 29.4kHz
              5. 6.3.7.2.5.1.5 Sampling Rate: 48kHz or 44.1kHz
              6. 6.3.7.2.5.1.6 Sampling Rate: 96kHz or 88.2kHz
              7. 6.3.7.2.5.1.7 Sampling Rate: 192kHz or 176.4kHz
            2. 6.3.7.2.5.2 Low-latency Filters
              1. 6.3.7.2.5.2.1 Sampling Rate: 24kHz or 22.05kHz
              2. 6.3.7.2.5.2.2 Sampling Rate: 32kHz or 29.4kHz
              3. 6.3.7.2.5.2.3 Sampling Rate: 48kHz or 44.1kHz
              4. 6.3.7.2.5.2.4 Sampling Rate: 96kHz or 88.2kHz
              5. 6.3.7.2.5.2.5 Sampling Rate: 192kHz or 176.4kHz
            3. 6.3.7.2.5.3 Ultra-Low-Latency Filters
              1. 6.3.7.2.5.3.1 Sampling Rate: 24kHz or 22.05kHz
              2. 6.3.7.2.5.3.2 Sampling Rate: 32kHz or 29.4kHz
              3. 6.3.7.2.5.3.3 Sampling Rate: 48kHz or 44.1kHz
              4. 6.3.7.2.5.3.4 Sampling Rate: 96kHz or 88.2kHz
              5. 6.3.7.2.5.3.5 Sampling Rate 192kHz or 176.4kHz
      8. 6.3.8 Interrupts, Status, and Digital I/O Pin Multiplexing
      9. 6.3.9 Power Tune Mode
    4. 6.4 Device Functional Modes
      1. 6.4.1 Sleep Mode or Software Shutdown
      2. 6.4.2 Software Reset
      3. 6.4.3 Active Mode
    5. 6.5 Programming
      1. 6.5.1 Control Serial Interfaces
        1. 6.5.1.1 General I2C Operation
        2. 6.5.1.2 I2C Single-Byte and Multiple-Byte Transfers
          1. 6.5.1.2.1 I2C Single-Byte Write
          2. 6.5.1.2.2 I2C Multiple-Byte Write
          3. 6.5.1.2.3 I2C Single-Byte Read
          4. 6.5.1.2.4 I2C Multiple-Byte Read
  8. 7 Register Maps
    1. 7.1 Device Configuration Registers
      1. 7.1.1 TAC5301-Q1_B0_P0 Registers
      2. 7.1.2 TAC5301-Q1_B0_P1 Registers
      3. 7.1.3 TAC5301-Q1_B0_P3 Registers
    2. 7.2 Programmable Coefficient Registers
      1. 7.2.1  Programmable Coefficient Registers: Page 8
      2. 7.2.2  Programmable Coefficient Registers: Page 9
      3. 7.2.3  Programmable Coefficient Registers: Page 10
      4. 7.2.4  Programmable Coefficient Registers: Page 11
      5. 7.2.5  Programmable Coefficient Registers: Page 15
      6. 7.2.6  Programmable Coefficient Registers: Page 16
      7. 7.2.7  Programmable Coefficient Registers: Page 17
      8. 7.2.8  Programmable Coefficient Registers: Page 18
      9. 7.2.9  Programmable Coefficient Registers: Page 19
      10. 7.2.10 Programmable Coefficient Registers: Page 25
      11. 7.2.11 Programmable Coefficient Registers: Page 26
      12. 7.2.12 Programmable Coefficient Registers: Page 27
      13. 7.2.13 Programmable Coefficient Registers: Page 28
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
      4. 8.2.4 Typical Characteristics
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 IOVDD_IO_MODE for 1.8V and 1.2V Operation
    4. 8.4 Layout
      1. 8.4.1 Layout Example
      2. 8.4.2 Layout Guidelines
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Electrostatic Discharge Caution
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

4 Pin Configuration and Functions

TAC5301-Q1 TAC5301-Q1 24-Pin QFN Package with Exposed Thermal Pad and Corner Pins,Top View Figure 4-1 TAC5301-Q1 24-Pin QFN Package with Exposed Thermal Pad and Corner Pins,Top View
Table 4-1 Pin Functions
PIN TYPE DESCRIPTION
NAME NO.
VSS A1 Ground Ground pin. Short directly to board ground plane.
DREG 1 Digital Supply Digital on-chip regulator output voltage for digital supply (1.5V, nominal)
BCLK 2 Digital I/O Audio serial data interface bus bit clock
FSYNC 3 Digital I/O Audio serial data interface bus frame synchronization signal
DOUT 4 Digital Output Audio serial data interface bus output
DIN 5 Digital Input Audio serial data interface bus input
IOVDD 6 Digital Supply Digital I/O power supply (1.2V or 1.8V or 3.3V, nominal)
IOVSS A2 Digital Ground Digital I/O supply ground pin. Short directly to board ground plane.
SCL 7 Digital Input Clock for I2C control interface
SDA 8 Digital I/O Data for I2C control interface
GPIO1 9 Digital I/O General-purpose digital input/output 1 (multipurpose functions such as daisy-chain input, audio data output, PLL input clock source, interrupt, and so forth)
VSSA 10 Ground Short directly to board ground plane
AVDD 11 Analog Supply Analog power supply (3.3V, nominal)
VSSA 12 Ground Short directly to board ground plane
AVSS A3 Ground Analog supply ground pin. Short directly to board ground plane.
HVDD 13 Analog Supply Analog power supply (up to 12V) for generating microphone bias voltage
MICBIAS 14 Analog MICBIAS output (Programmable output up to 10V)
IN1P 15 Analog Input Analog input 1P pin
IN1M 16 Analog Input Analog input 1M pin
IN2P 17 Analog Input Analog input 2P pin
IN2M 18 Analog Input Analog input 2M pin
AVSS A4 Ground Analog supply ground pin. Short directly to board ground plane.
OUT1M 19 Analog Output Analog output 1M pin
OUT1P 20 Analog Output Analog output 1P pin
OUT2P 21 Analog Output Analog output 2P pin
OUT2M 22 Analog Output Analog output 2M pin
AVDD 23 Analog Supply Analog power supply (3.3V, nominal)
VREF 24 Analog Analog reference voltage filter output
VSS Thermal Pad Ground Thermal pad shorted to internal device ground. Short directly to the board ground plane