SLASFD9 April   2025 TAC5301-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Electrical Characteristics
    7. 5.7  Timing Requirements: I2C Interface
    8. 5.8  Switching Characteristics: I2C Interface
    9. 5.9  Timing Requirements: TDM, I2S or LJ Interface
    10. 5.10 Switching Characteristics: TDM, I2S or LJ Interface
    11. 5.11 Timing Diagrams
    12. 5.12 Typical Charactaristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Serial Interfaces
        1. 6.3.1.1 Control Serial Interfaces
        2. 6.3.1.2 Audio Serial Interfaces
          1. 6.3.1.2.1 Time Division Multiplexed Audio (TDM) Interface
          2. 6.3.1.2.2 Inter IC Sound (I2S) Interface
          3. 6.3.1.2.3 Left-Justified (LJ) Interface
        3. 6.3.1.3 Using Multiple Devices With Shared Buses
      2. 6.3.2 Phase-Locked Loop (PLL) and Clock Generation
      3. 6.3.3 Input Channel Configuration
      4. 6.3.4 Output Channel Configurations
      5. 6.3.5 Reference Voltage
      6. 6.3.6 Microphone Bias
      7. 6.3.7 Signal-Chain Processing
        1. 6.3.7.1 ADC Signal-Chain
          1. 6.3.7.1.1  Programmable Channel Gain and Digital Volume Control
          2. 6.3.7.1.2  Programmable Channel Gain Calibration
          3. 6.3.7.1.3  Programmable Channel Phase Calibration
          4. 6.3.7.1.4  Programmable Digital High-Pass Filter
          5. 6.3.7.1.5  Programmable Digital Biquad Filters
          6. 6.3.7.1.6  Programmable Channel Summer and Digital Mixer
          7. 6.3.7.1.7  Configurable Digital Decimation Filters
            1. 6.3.7.1.7.1 Linear-phase filters
              1. 6.3.7.1.7.1.1 Sampling Rate: 8kHz or 7.35kHz
              2. 6.3.7.1.7.1.2 Sampling Rate: 16kHz or 14.7kHz
              3. 6.3.7.1.7.1.3 Sampling Rate: 24kHz or 22.05kHz
              4. 6.3.7.1.7.1.4 Sampling Rate: 32kHz or 29.4kHz
              5. 6.3.7.1.7.1.5 Sampling Rate: 48kHz or 44.1kHz
              6. 6.3.7.1.7.1.6 Sampling Rate: 96kHz or 88.2kHz
              7. 6.3.7.1.7.1.7 Sampling Rate: 192kHz or 176.4kHz
            2. 6.3.7.1.7.2 Low-latency Filters
              1. 6.3.7.1.7.2.1 Sampling Rate: 24kHz or 22.05kHz
              2. 6.3.7.1.7.2.2 Sampling Rate: 32kHz or 29.4kHz
              3. 6.3.7.1.7.2.3 Sampling Rate: 48kHz or 44.1kHz
              4. 6.3.7.1.7.2.4 Sampling Rate: 96kHz or 88.2kHz
              5. 6.3.7.1.7.2.5 Sampling Rate: 192kHz or 176.4kHz
            3. 6.3.7.1.7.3 Ultra-Low-Latency Filters
              1. 6.3.7.1.7.3.1 Sampling Rate: 24kHz or 22.05kHz
              2. 6.3.7.1.7.3.2 Sampling Rate: 32kHz or 29.4kHz
              3. 6.3.7.1.7.3.3 Sampling Rate: 48kHz or 44.1kHz
              4. 6.3.7.1.7.3.4 Sampling Rate: 96kHz or 88.2kHz
              5. 6.3.7.1.7.3.5 Sampling Rate: 192kHz or 176.4kHz
          8. 6.3.7.1.8  Automatic Gain Controller (AGC)
          9. 6.3.7.1.9  Voice Activity Detection (VAD)
          10. 6.3.7.1.10 Ultrasonic Activity Detection (UAD)
        2. 6.3.7.2 DAC Signal-Chain
          1. 6.3.7.2.1 Programmable Channel Gain and Digital Volume Control
          2. 6.3.7.2.2 Programmable Channel Gain Calibration
          3. 6.3.7.2.3 Programmable Digital High-Pass Filter
          4. 6.3.7.2.4 Programmable Digital Biquad Filters
          5. 6.3.7.2.5 Configurable Digital Interpolation Filters
            1. 6.3.7.2.5.1 Linear-phase filters
              1. 6.3.7.2.5.1.1 Sampling Rate: 8kHz or 7.35kHz
              2. 6.3.7.2.5.1.2 Sampling Rate: 16kHz or 14.7kHz
              3. 6.3.7.2.5.1.3 Sampling Rate: 24kHz or 22.05kHz
              4. 6.3.7.2.5.1.4 Sampling Rate: 32kHz or 29.4kHz
              5. 6.3.7.2.5.1.5 Sampling Rate: 48kHz or 44.1kHz
              6. 6.3.7.2.5.1.6 Sampling Rate: 96kHz or 88.2kHz
              7. 6.3.7.2.5.1.7 Sampling Rate: 192kHz or 176.4kHz
            2. 6.3.7.2.5.2 Low-latency Filters
              1. 6.3.7.2.5.2.1 Sampling Rate: 24kHz or 22.05kHz
              2. 6.3.7.2.5.2.2 Sampling Rate: 32kHz or 29.4kHz
              3. 6.3.7.2.5.2.3 Sampling Rate: 48kHz or 44.1kHz
              4. 6.3.7.2.5.2.4 Sampling Rate: 96kHz or 88.2kHz
              5. 6.3.7.2.5.2.5 Sampling Rate: 192kHz or 176.4kHz
            3. 6.3.7.2.5.3 Ultra-Low-Latency Filters
              1. 6.3.7.2.5.3.1 Sampling Rate: 24kHz or 22.05kHz
              2. 6.3.7.2.5.3.2 Sampling Rate: 32kHz or 29.4kHz
              3. 6.3.7.2.5.3.3 Sampling Rate: 48kHz or 44.1kHz
              4. 6.3.7.2.5.3.4 Sampling Rate: 96kHz or 88.2kHz
              5. 6.3.7.2.5.3.5 Sampling Rate 192kHz or 176.4kHz
      8. 6.3.8 Interrupts, Status, and Digital I/O Pin Multiplexing
      9. 6.3.9 Power Tune Mode
    4. 6.4 Device Functional Modes
      1. 6.4.1 Sleep Mode or Software Shutdown
      2. 6.4.2 Software Reset
      3. 6.4.3 Active Mode
    5. 6.5 Programming
      1. 6.5.1 Control Serial Interfaces
        1. 6.5.1.1 General I2C Operation
        2. 6.5.1.2 I2C Single-Byte and Multiple-Byte Transfers
          1. 6.5.1.2.1 I2C Single-Byte Write
          2. 6.5.1.2.2 I2C Multiple-Byte Write
          3. 6.5.1.2.3 I2C Single-Byte Read
          4. 6.5.1.2.4 I2C Multiple-Byte Read
  8. 7 Register Maps
    1. 7.1 Device Configuration Registers
      1. 7.1.1 TAC5301-Q1_B0_P0 Registers
      2. 7.1.2 TAC5301-Q1_B0_P1 Registers
      3. 7.1.3 TAC5301-Q1_B0_P3 Registers
    2. 7.2 Programmable Coefficient Registers
      1. 7.2.1  Programmable Coefficient Registers: Page 8
      2. 7.2.2  Programmable Coefficient Registers: Page 9
      3. 7.2.3  Programmable Coefficient Registers: Page 10
      4. 7.2.4  Programmable Coefficient Registers: Page 11
      5. 7.2.5  Programmable Coefficient Registers: Page 15
      6. 7.2.6  Programmable Coefficient Registers: Page 16
      7. 7.2.7  Programmable Coefficient Registers: Page 17
      8. 7.2.8  Programmable Coefficient Registers: Page 18
      9. 7.2.9  Programmable Coefficient Registers: Page 19
      10. 7.2.10 Programmable Coefficient Registers: Page 25
      11. 7.2.11 Programmable Coefficient Registers: Page 26
      12. 7.2.12 Programmable Coefficient Registers: Page 27
      13. 7.2.13 Programmable Coefficient Registers: Page 28
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
      4. 8.2.4 Typical Characteristics
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 IOVDD_IO_MODE for 1.8V and 1.2V Operation
    4. 8.4 Layout
      1. 8.4.1 Layout Example
      2. 8.4.2 Layout Guidelines
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Electrostatic Discharge Caution
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

6.3.6 Microphone Bias

The device integrates a built-in, low-noise, programmable, high-voltage, microphone bias pin (MICBIAS) that can be used in the system for biasing the analog microphones. The integrated bias amplifier supports up to 30mA of load current, which can be used for multiple microphones and is designed to provide a combination of high PSRR, low noise, and programmable bias voltages to allow the biasing to be fine tuned for specific microphone combinations. The TAC5301-Q1 uses an external high voltage supply (HVDD) for generating the programmable microphone bias. The minimum voltage must be 0.6V higher than the programmed MICBIAS value

When using the MICBIAS pin for biasing multiple microphones, TI recommends avoiding common impedance on the board layout for the MICBIAS connection to minimize coupling across microphones. Section 6.3.6 shows the available microphone bias programmable options.

Table 6-11 MICBIAS Programmable Settings
P1_R115_D[7:4] : MBIAS_VAL[3:0]MICBIAS OUTPUT VOLTAGE
0000 Bypass
0001Set to 3.0V
0010Set to 3.5V
0011-1000Set to 4.0V- 6.5V
1001Set to 7.0V
1010Set to 7.5V (default)
1011Set to 8.0V
1100Set to 8.5V
1101Set to 9.0V
1110Set to 9.5V
1111Set to 10.0V

The microphone bias output can be powered on or powered off (default) by configuring the MICBIAS_PDZ, P0_R120_D[5] register bit. Additionally, the device provides an option to configure the GPIO1 pins to directly control the microphone bias output power on or power off. This feature is useful in some systems to control the microphone directly without engaging the host for I2C communication. The MICBIAS_PDZ, P0_R120_D[5] register bit value is ignored if the GPIO1 pins are configured to control the microphone bias power on or power off.