SLASFD9 April   2025 TAC5301-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Electrical Characteristics
    7. 5.7  Timing Requirements: I2C Interface
    8. 5.8  Switching Characteristics: I2C Interface
    9. 5.9  Timing Requirements: TDM, I2S or LJ Interface
    10. 5.10 Switching Characteristics: TDM, I2S or LJ Interface
    11. 5.11 Timing Diagrams
    12. 5.12 Typical Charactaristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Serial Interfaces
        1. 6.3.1.1 Control Serial Interfaces
        2. 6.3.1.2 Audio Serial Interfaces
          1. 6.3.1.2.1 Time Division Multiplexed Audio (TDM) Interface
          2. 6.3.1.2.2 Inter IC Sound (I2S) Interface
          3. 6.3.1.2.3 Left-Justified (LJ) Interface
        3. 6.3.1.3 Using Multiple Devices With Shared Buses
      2. 6.3.2 Phase-Locked Loop (PLL) and Clock Generation
      3. 6.3.3 Input Channel Configuration
      4. 6.3.4 Output Channel Configurations
      5. 6.3.5 Reference Voltage
      6. 6.3.6 Microphone Bias
      7. 6.3.7 Signal-Chain Processing
        1. 6.3.7.1 ADC Signal-Chain
          1. 6.3.7.1.1  Programmable Channel Gain and Digital Volume Control
          2. 6.3.7.1.2  Programmable Channel Gain Calibration
          3. 6.3.7.1.3  Programmable Channel Phase Calibration
          4. 6.3.7.1.4  Programmable Digital High-Pass Filter
          5. 6.3.7.1.5  Programmable Digital Biquad Filters
          6. 6.3.7.1.6  Programmable Channel Summer and Digital Mixer
          7. 6.3.7.1.7  Configurable Digital Decimation Filters
            1. 6.3.7.1.7.1 Linear-phase filters
              1. 6.3.7.1.7.1.1 Sampling Rate: 8kHz or 7.35kHz
              2. 6.3.7.1.7.1.2 Sampling Rate: 16kHz or 14.7kHz
              3. 6.3.7.1.7.1.3 Sampling Rate: 24kHz or 22.05kHz
              4. 6.3.7.1.7.1.4 Sampling Rate: 32kHz or 29.4kHz
              5. 6.3.7.1.7.1.5 Sampling Rate: 48kHz or 44.1kHz
              6. 6.3.7.1.7.1.6 Sampling Rate: 96kHz or 88.2kHz
              7. 6.3.7.1.7.1.7 Sampling Rate: 192kHz or 176.4kHz
            2. 6.3.7.1.7.2 Low-latency Filters
              1. 6.3.7.1.7.2.1 Sampling Rate: 24kHz or 22.05kHz
              2. 6.3.7.1.7.2.2 Sampling Rate: 32kHz or 29.4kHz
              3. 6.3.7.1.7.2.3 Sampling Rate: 48kHz or 44.1kHz
              4. 6.3.7.1.7.2.4 Sampling Rate: 96kHz or 88.2kHz
              5. 6.3.7.1.7.2.5 Sampling Rate: 192kHz or 176.4kHz
            3. 6.3.7.1.7.3 Ultra-Low-Latency Filters
              1. 6.3.7.1.7.3.1 Sampling Rate: 24kHz or 22.05kHz
              2. 6.3.7.1.7.3.2 Sampling Rate: 32kHz or 29.4kHz
              3. 6.3.7.1.7.3.3 Sampling Rate: 48kHz or 44.1kHz
              4. 6.3.7.1.7.3.4 Sampling Rate: 96kHz or 88.2kHz
              5. 6.3.7.1.7.3.5 Sampling Rate: 192kHz or 176.4kHz
          8. 6.3.7.1.8  Automatic Gain Controller (AGC)
          9. 6.3.7.1.9  Voice Activity Detection (VAD)
          10. 6.3.7.1.10 Ultrasonic Activity Detection (UAD)
        2. 6.3.7.2 DAC Signal-Chain
          1. 6.3.7.2.1 Programmable Channel Gain and Digital Volume Control
          2. 6.3.7.2.2 Programmable Channel Gain Calibration
          3. 6.3.7.2.3 Programmable Digital High-Pass Filter
          4. 6.3.7.2.4 Programmable Digital Biquad Filters
          5. 6.3.7.2.5 Configurable Digital Interpolation Filters
            1. 6.3.7.2.5.1 Linear-phase filters
              1. 6.3.7.2.5.1.1 Sampling Rate: 8kHz or 7.35kHz
              2. 6.3.7.2.5.1.2 Sampling Rate: 16kHz or 14.7kHz
              3. 6.3.7.2.5.1.3 Sampling Rate: 24kHz or 22.05kHz
              4. 6.3.7.2.5.1.4 Sampling Rate: 32kHz or 29.4kHz
              5. 6.3.7.2.5.1.5 Sampling Rate: 48kHz or 44.1kHz
              6. 6.3.7.2.5.1.6 Sampling Rate: 96kHz or 88.2kHz
              7. 6.3.7.2.5.1.7 Sampling Rate: 192kHz or 176.4kHz
            2. 6.3.7.2.5.2 Low-latency Filters
              1. 6.3.7.2.5.2.1 Sampling Rate: 24kHz or 22.05kHz
              2. 6.3.7.2.5.2.2 Sampling Rate: 32kHz or 29.4kHz
              3. 6.3.7.2.5.2.3 Sampling Rate: 48kHz or 44.1kHz
              4. 6.3.7.2.5.2.4 Sampling Rate: 96kHz or 88.2kHz
              5. 6.3.7.2.5.2.5 Sampling Rate: 192kHz or 176.4kHz
            3. 6.3.7.2.5.3 Ultra-Low-Latency Filters
              1. 6.3.7.2.5.3.1 Sampling Rate: 24kHz or 22.05kHz
              2. 6.3.7.2.5.3.2 Sampling Rate: 32kHz or 29.4kHz
              3. 6.3.7.2.5.3.3 Sampling Rate: 48kHz or 44.1kHz
              4. 6.3.7.2.5.3.4 Sampling Rate: 96kHz or 88.2kHz
              5. 6.3.7.2.5.3.5 Sampling Rate 192kHz or 176.4kHz
      8. 6.3.8 Interrupts, Status, and Digital I/O Pin Multiplexing
      9. 6.3.9 Power Tune Mode
    4. 6.4 Device Functional Modes
      1. 6.4.1 Sleep Mode or Software Shutdown
      2. 6.4.2 Software Reset
      3. 6.4.3 Active Mode
    5. 6.5 Programming
      1. 6.5.1 Control Serial Interfaces
        1. 6.5.1.1 General I2C Operation
        2. 6.5.1.2 I2C Single-Byte and Multiple-Byte Transfers
          1. 6.5.1.2.1 I2C Single-Byte Write
          2. 6.5.1.2.2 I2C Multiple-Byte Write
          3. 6.5.1.2.3 I2C Single-Byte Read
          4. 6.5.1.2.4 I2C Multiple-Byte Read
  8. 7 Register Maps
    1. 7.1 Device Configuration Registers
      1. 7.1.1 TAC5301-Q1_B0_P0 Registers
      2. 7.1.2 TAC5301-Q1_B0_P1 Registers
      3. 7.1.3 TAC5301-Q1_B0_P3 Registers
    2. 7.2 Programmable Coefficient Registers
      1. 7.2.1  Programmable Coefficient Registers: Page 8
      2. 7.2.2  Programmable Coefficient Registers: Page 9
      3. 7.2.3  Programmable Coefficient Registers: Page 10
      4. 7.2.4  Programmable Coefficient Registers: Page 11
      5. 7.2.5  Programmable Coefficient Registers: Page 15
      6. 7.2.6  Programmable Coefficient Registers: Page 16
      7. 7.2.7  Programmable Coefficient Registers: Page 17
      8. 7.2.8  Programmable Coefficient Registers: Page 18
      9. 7.2.9  Programmable Coefficient Registers: Page 19
      10. 7.2.10 Programmable Coefficient Registers: Page 25
      11. 7.2.11 Programmable Coefficient Registers: Page 26
      12. 7.2.12 Programmable Coefficient Registers: Page 27
      13. 7.2.13 Programmable Coefficient Registers: Page 28
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
      4. 8.2.4 Typical Characteristics
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 IOVDD_IO_MODE for 1.8V and 1.2V Operation
    4. 8.4 Layout
      1. 8.4.1 Layout Example
      2. 8.4.2 Layout Guidelines
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Electrostatic Discharge Caution
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5.6 Electrical Characteristics

At TA = 25°C, AVDD = 3.3V, IOVDD = 3.3V, HVDD = 11V, fIN = 1kHz sinusoidal signal, fS = 48kHz, 32-bit audio data, BCLK = 256 x fS, TDM target mode, PLL on, channel gain = 0dB, linear phase decimation/interpolation filters, AC-coupled differential input with VCM = 1.414V, 1200Ω/600Ω line-out load in differential/ single-ended configuration or 32Ω/16Ω receiver/headphone load as applicable and other default configurations; measured filter free with an audio precision with a 20Hz to a 20kHz un-weighted bandwidth, unless otherwise noted
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
ADC PERFORMANCE FOR LINE/MIC INPUT RECORDING
Differential input full-scale DC signal voltage AC-coupled or DC-coupled input 2 VRMS
Single-ended input full-scale DC signal voltage AC-coupled or DC-coupled input 1 VRMS
ADC PERFORMANCE FOR LINE/MIC INPUT RECORDING
SNR Signal-to-noise ratio, A-weighted(1)(2)
IN1x differential DC-coupled input and AC signal
shorted to ground, 0dB channel gain

 101 dB

IN1x differential DC-coupled input and AC signal
shorted to ground, 12dB channel gain

89
SNR Signal-to-noise ratio, A-weighted(1)(2) Wideband Mode(3): IN1x differential DC-coupled input and AC signal shorted to ground, 0dB channel gain (Integrated till 20kHz) 101 dB
SNR Signal-to-noise ratio, A-weighted(1)(2) Power Tune Mode(4): IN1x differential DC-coupled input and AC signal shorted to ground, 0dB channel gain 99 dB
DR Dynamic range, A-weighted(2)
IN1x differential DC-coupled input and –60dBFS
AC signal input, 0dB channel gain

 100 dB

IN1x differential DC-coupled input and –72dBFS
AC signal input, 12dB channel gain

 88
DR Dynamic range, A-weighted(2) Power Tune Mode(4): IN1x differential DC-coupled input and –60dBFS AC signal input, 0dB channel gain 98 dB
THD+N Total harmonic distortion(2) IN1x differential DC-coupled input and –1dBFS AC signal input, 0dB channel gain -87 dB
IN1x differential DC-coupled input and –13dBFS AC signal input, 12dB channel gain   -85
AC Input impedance Input pins INxP or INxM 34 kΩ
Digital volume control range Programmable 0.5dB steps –80 47 dB
Input Signal Bandwidth Upto 192KSPS FS Rate 0.46 FS
>192KSPS 85 kHz
Output data sample rate Programmable 4 768 kHz
Output data sample word length Programmable 16 32 Bits
Digital high-pass filter cutoff frequency First-order IIR filter with programmable coefficients, –3dB point (default setting) 1 Hz
PSRR Power-supply rejection ratio 100mVPP, 1kHz sinusoidal signal on AVDD, differential input, 0dB channel gain 92 dB
CMRR Common-mode rejection ratio
Differential DC-coupled input, 0dB channel gain,
–6dBFS AC input, 1kHz signal on both pins and
measured level at output


 60 dB
MICROPHONE BIAS
MICBIAS noise BW = 20 Hz to 20 kHz, A-weighted, 1µF capacitor between MICBIAS and AVSS 20 µVRMS
MICBIAS voltage Programmable 0.5V steps 3 10 V
MICBIAS current drive MICBIAS voltage 10V 30 mA
MICBIAS load regulation MICBIAS voltage 10V, measured up to maximum load 0 1 %
MICBIAS over current protection threshold MICBIAS voltage 10V 32 mA
DIGITAL I/O
VIL Low-level digital input logic voltage threshold All digital pins except SDA and SCL, IOVDD 1.8V or 1.2V operation –0.3 0.35 x IOVDD V
All digital pins except SDA and SCL, IOVDD 3.3V operation –0.3 0.8
VIH High-level digital input logic voltage threshold All digital pins except SDA and SCL, IOVDD 1.8V or 1.2V operation 0.65 x IOVDD IOVDD + 0.3 V
All digital pins except SDA and SCL, IOVDD 3.3V operation 2 IOVDD + 0.3
VOL Low-level digital output voltage All digital pins except SDA and SCL, IOL = –2mA, IOVDD 1.8V or 1.2V operation 0.45 V
All digital pins except SDA and SCL, IOL = –2mA, IOVDD 3.3V operation 0.4
VOH High-level digital output voltage All digital pins except SDA and SCL, IOH = 2mA, IOVDD 1.8V or 1.2V operation IOVDD – 0.45 V
All digital pins except SDA and SCL, IOH = 2mA, IOVDD 3.3V operation 2.4
VIL(I2C) Low-level digital input logic voltage threshold SDA and SCL –0.5 0.3 x IOVDD V
VIH(I2C) High-level digital input logic voltage threshold SDA and SCL 0.7 x IOVDD IOVDD + 0.5 V
VOL1(I2C) Low-level digital output voltage SDA, IOL(I2C) = –3mA, IOVDD 3.3V operation 0.4 V
VOL2(I2C) Low-level digital output voltage SDA, IOL(I2C) = –2mA, IOVDD 1.8V or 1.2V operation 0.2 x IOVDD V
IOL(I2C) Low-level digital output current SDA, VOL(I2C) = 0.4V, standard-mode or fast-mode 3 mA
SDA, VOL(I2C) = 0.4V, fast-mode plus 20
IIL Input logic-low leakage for digital inputs All digital pins, input = 0V –5 0.1 5 µA
IIH Input logic-high leakage for digital inputs All digital pins, input = IOVDD –5 0.1 5 µA
CIN Input capacitance for digital inputs All digital pins 5 pF
RPD Pulldown resistance for digital I/O pins when asserted on 20 kΩ
TYPICAL SUPPLY CURRENT CONSUMPTION
IAVDD Current consumption in sleep mode (software shutdown mode) All device external clocks stopped 9 µA
IHVDD 0.01
IIOVDD 1
IAVDD Current consumption with MICBIAS ON, MICBIAS voltage 10V, 30 mA load, ADC off fS = 48kHz, BCLK = 256 × fS 1.6 mA
IHVDD 1.1
IIOVDD 0.02
IAVDD Current consumption with ADC 1-channel operation with MICBIAS off, PLL on fS = 16kHz, BCLK = 512 × fS 6.3 mA
IIOVDD 0.1
IAVDD Current consumption with ADC 1-channel operation with MICBIAS on, PLL off fS = 48kHz, BCLK = 512 × fS 5.7 mA
IHVDD 1.1
IIOVDD 0.3
IAVDD Current consumption with DAC to HP 1-channel operation with MICBIAS off, PLL on fS = 16kHz, BCLK = 512 × fS 12.1 mA
IIOVDD 0.02
IAVDD Current consumption with DAC to HP 1-channel operation with MICBIAS off, PLL off fS = 48kHz, BCLK = 512 × fS 9.5 mA
IIOVDD 0.04
IAVDD Current consumption with ADC 1-channel operation and DAC to HP 1-channel operation with MICBIAS off, PLL off fS = 48kHz, BCLK = 512 × fS 24.5 mA
IHVDD 1.1
IIOVDD 0.3
IAVDD Power Tune Mode(4): Current consumption with DAC to LO SE 1-channel operation with MICBIAS off, PLL off fS = 48kHz, BCLK = 512 × fS 7.2 mA
IIOVDD 0.04
IAVDD Power Tune Mode(4): Current consumption with ADC 1-channel with MICBIAS off, PLL off fS = 48kHz, BCLK = 128 × fS 3.6 mA
IIOVDD 0.2
(1) Ratio of output level with 1kHz full-scale sine-wave input, to the output level with the AC signal input shorted to ground or no generator input signal, measured A-weighted over a 20Hz to 20kHz bandwidth using an audio analyzer.
(2) All performance measurements done with 20kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter can result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes out-of-band noise, which, although not audible, can affect dynamic specification values.
(3) ADC_CHx_BW_MODE = 1'b1 for Wideband Mode
(4) PWR_TUNE_CFG0 = 0xD4, PWR_TUNE_CFG1 = 0x96 and PLL_DIS = 1'b1 for Power Tune Mode