SLAU319AF July   2010  – September 2022

 

  1.   Abstract - MSP430™ Flash Devices Bootloader (BSL)
  2.   Trademarks
  3. 1Introduction
    1. 1.1 Supplementary Online Information
    2. 1.2 Overview of BSL Features
    3. 1.3 BSL Invocation
      1. 1.3.1 Hardware BSL Invocation
        1. 1.3.1.1 MSP430 Devices With Shared JTAG Pins
          1. 1.3.1.1.1 Factors That Prevent BSL Invocation With Shared JTAG Pins
        2. 1.3.1.2 MSP430 Flash Devices With Dedicated JTAG Pins
          1. 1.3.1.2.1 Factors That Prevent BSL Invocation With Dedicated JTAG Pins
        3. 1.3.1.3 Devices With USB
      2. 1.3.2 Software BSL Invocation
    4. 1.4 UART Protocol
    5. 1.5 USB Protocol
  4. 2Bootloader Protocol – 1xx, 2xx, and 4xx Families
    1. 2.1 Synchronization Sequence
    2. 2.2 Commands
      1. 2.2.1 Unprotected Commands
      2. 2.2.2 Password Protected Commands
    3. 2.3 Programming Flow
    4. 2.4 Data Frame
      1. 2.4.1 Data-Stream Structure
      2. 2.4.2 Checksum
      3. 2.4.3 Example Sequence
      4. 2.4.4 Commands – Detailed Description
        1. 2.4.4.1  General
        2. 2.4.4.2  RX Data Block
        3. 2.4.4.3  RX Password
        4. 2.4.4.4  Mass Erase
        5. 2.4.4.5  Erase Segment
        6. 2.4.4.6  Erase Main or Info
        7. 2.4.4.7  Erase Check
        8. 2.4.4.8  Change Baud Rate
        9. 2.4.4.9  Set Memory Offset
        10. 2.4.4.10 Load PC
        11. 2.4.4.11 TX Data Block
        12. 2.4.4.12 TX BSL Version
    5. 2.5 Loadable BSL
    6. 2.6 Exiting the BSL
    7. 2.7 Password Protection
    8. 2.8 Code Protection Fuse
    9. 2.9 BSL Internal Settings and Resources
      1. 2.9.1 Chip Identification and BSL Version
      2. 2.9.2 Vectors to Call the BSL Externally
      3. 2.9.3 Initialization Status
      4. 2.9.4 Memory Allocation and Resources
  5. 3Bootloader Protocol – F5xx and F6xx Families
    1. 3.1 BSL Data Packet
    2. 3.2 UART Peripheral Interface (PI)
      1. 3.2.1 Wrapper
      2. 3.2.2 Abbreviations
      3. 3.2.3 Messages
      4. 3.2.4 Interface Specific Commands
        1. 3.2.4.1 Change Baud Rate
    3. 3.3 I2C Peripheral Interface
      1. 3.3.1 I2C Protocol Definition
      2. 3.3.2 Basic Protocol With Byte Level Acknowledge
      3. 3.3.3 I2C Protocol for BSL - Read From Slave
      4. 3.3.4 Acknowledge (ACK)
      5. 3.3.5 Wrapper
    4. 3.4 USB Peripheral Interface
      1. 3.4.1 Wrapper
      2. 3.4.2 Hardware Requirements
    5. 3.5 BSL Core Command Structure
      1. 3.5.1 Abbreviations
      2. 3.5.2 Command Descriptions
    6. 3.6 BSL Security
      1. 3.6.1 Protected Commands
      2. 3.6.2 RAM Erase
    7. 3.7 BSL Core Responses
      1. 3.7.1 Abbreviations
      2. 3.7.2 BSL Core Messages
      3. 3.7.3 BSL Version Number
      4. 3.7.4 Example Sequences for UART BSL
    8. 3.8 BSL Public Functions and Z-Area
      1. 3.8.1 Starting the BSL From an External Application
      2. 3.8.2 Return to BSL Function Description
  6. 4Bootloader Hardware
    1. 4.1 Hardware Description
      1. 4.1.1 Power Supply
      2. 4.1.2 Serial Interface
        1. 4.1.2.1 Level Shifting
        2. 4.1.2.2 Control of RST/NMI and TEST or TCK Pins
      3. 4.1.3 Target Connector
      4. 4.1.4 Parts List
  7. 5Differences Between Devices and Bootloader Versions
    1. 5.1 1xx, 2xx, and 4xx BSL Versions
    2. 5.2 Special Consideration for ROM BSL Version 1.10
    3. 5.3 1xx, 2xx, and 4xx BSL Known Issues
    4. 5.4 Special Note on the MSP430F14x Device Family BSL
    5. 5.5 F5xx and F6xx Flash-Based BSL Versions
  8. 6Bootloader PCB Layout Suggestion
  9. 7Revision History

5.1 1xx, 2xx, and 4xx BSL Versions

The tables in this section show the key information of MSP430 device to BSL version assignment related to their hardware and software resources.

Table 5-1 BSL Version 1.10 on F13x, F14x(1) (excluding Rev AA), F11x, and F11x1
Device F13x
F14x(1) up to Rev N		 F11x (obsolete)
F11x1 (obsolete)
BSL Version 1.10
BSL vector address Cold start 0C00h
Warm start —
Chip ID address 0FF0h
Chip ID data F149h F112h
BSL version address 0FFAh
BSL version data 0110h
Mass erase time, nominal (ms) 17.2(1)
Read and write access at 0000h to FFFFh Byte
Verification during write (online) No
Stack pointer initialization SP critical 021Ah
SP not critical Unchanged
Resources Used by BSL
Transmit pin (TX), Receive pin (RX) P1.1, P2.2
RAM stack used 0200h to 0219h
Working registers R5 to R9
System clock, affected controls BCSCTL1, DCOCTL
Timer_A, affected controls TACTL, TAR, CCTL0, CCR0
Preparation for software call 
mov    #00h, &CCTL0
bic.b  #02h, &P1SEL
bic.b  #04h, &P2SEL
bic.b  #32h, &IE1
mov.b  #00h, &BCSCTL2
mov    #00h, SR
br     &0C00h
Comment 1
Workaround mandatory		 Load PATCH.TXT to eliminate ROM bug (see Section 5.2 and Section 2.5).
Comment 2
Optional for F148, F149 only: Use loadable BSL
(>1 KB RAM required)		 Load BL_150S_14x.txt to get all features of V1.60 plus valid erase segment command (see Section 2.5).
Comment 3
Optional for F1x4 to F1x9: Use small loadable BSL
(<512B RAM required)		 Load BS_150S_14x.txt to get some features of V1.60 (see Section 2.5).
(1) To reach the required mass erase time as specified in the data sheet, the mass erase command must be executed several times.
Table 5-2 BSL Version 1.30 on F41x, F11x, and F11x1
Device F41x F11x (obsolete)
F11x1A
BSL Version 1.30
BSL vector address Cold start 0C00h
Warm start 0C02h
Chip ID address 0FF0h
Chip ID data F143h F112h
BSL version address 0FFAh
BSL version data 0130h
Mass erase time, nominal (ms) 206.4
Read and write access at 0000h to 00FFh Byte
0100h to FFFEh Word
Verification during write (online) No
Stack pointer initialization Cold start 0220h
Warm start Unchanged
Resources Used by BSL
Transmit pin (TX) P1.0 P1.1
Receive pin (RX) P2.1 P2.2
RAM stack used 0200h to 021Fh
Working registers R5 to R9
System clock, affected controls SCFI0, SCFI1, SCFQCTL BCSCTL1, DCOCTL
Timer_A, affected controls TACTL, TAR, CCTL0, CCR0
Preparation for software call 
mov    #00h, &CCTL0
mov.b  #00h, &FLLCTL1
br     &0C00h
 
mov    #00h, &CCTL0
mov.b  #00h, &BCSCTL2
mov    #00h, SR
br     &0C00h
Table 5-3 BSL Version 1.40 on F12x
Device F122, F123x
BSL Version 1.40
BSL vector address Cold start 0C00h
Warm start 0C02h
Chip ID address 0FF0h
Chip ID data F123h
BSL version address 0FFAh
BSL version data 0140h
Mass erase time, nominal (ms) 206.4
Read and write access at 0000h to 00FFh Byte
0100h to FFFEh Word
Verification during write (online) For addresses 0200h to FFFEh
Stack pointer initialization Cold start 0220h
Warm start Unchanged
Resources Used by BSL
Transmit pin (TX) P1.1
Receive pin (RX) P2.2
RAM stack used 0200h to 021Fh
Working registers R5 to R10
System clock, affected controls BCSCTL1, DCOCTL
Timer_A, affected controls TACTL, TAR, CCTL0, CCR0
Preparation for software call 
mov.b  #00h, &BCSCTL2
mov    #00h, SR
br     &0C00h
Table 5-4 BSL Version 1.60 on F11x2, F12x2, F43x, F44x, FE42x, FW42x, F43x, FG43x, F415, F417
Device F1122,
F1132		 F1222,
F1232		 F43x,
F44x		 FE42x,
FW42x,
F415,
F417		 F43x,
FG43x
BSL Version 1.60
BSL vector address Cold start 0C00h
Warm start 0C02h
Chip ID address 0FF0h
Chip ID data 1132h 1232h F449h F427h F439h
BSL version address 0FFAh
BSL version data 0160h
Mass erase time, nominal (ms) 206.4
Read and write access at 0000h to 00FFh Byte
0100h to FFFEh Word
Verification during write (online) For addresses 0200h to FFFEh
Erase check command Yes (error address 0200h)
Erase segment command With erasure verification (error address 0200h)
TX identification command Yes
Change baud rate command Yes
Stack pointer initialization Cold start 0220h
Warm start Unchanged
Resources Used by BSL
Transmit pin (TX) P1.1 P1.0
Receive pin (RX) P2.2 P1.1
RAM stack used 0200h to 021Fh
Working registers R5 to R12
System clock, affected controls BCSCTL1, DCOCTL SCFI0, SCFI1, SCFQCTL
Timer_A, affected controls TACTL, TAR, CCTL0, CCR0
Preparation for software call 
mov.b #00h, &BCSCTL2
mov #00h, SR
br &0C00h
 
mov.b #00h, &FLLCTL1
br    &0C00h
Comment Erase segment command Addresses 1000h to 11FFh are verified coherently (three segments). Also use erase check command.
Table 5-5 BSL Version 1.61 on F16x, F161x, F42x0, F13x rev AA, F14x(1) rev AA, F47x, FG47x
Device F16x F161x F149 Rev AA F42x0 F41x2 F47197 FG47x
BSL Version 1.61
BSL vector address Cold start 0C00h
Warm start 0C02h
Chip ID address 0FF0h
Chip ID data 0F169h 0F16Ch F149h F427h 4152h F47Fh 0F479h
BSL version address 0FFAh
BSL version data 0161h
Mass erase time, nominal (ms) 206.4
Read and write access at 0000h to 00FFh Byte
0100h to FFFEh Word
Verification during write (online) For addresses 0200h to FFFEh
Erase check command Yes (error address 0200h)
Erase segment command With erasure verification (error address 0200h)
TX identification command Yes
Change baud rate command Yes
Stack pointer initialization Cold start 0220h
Warm start Unchanged
Resources Used by BSL
Transmit pin (TX) P1.1 P1.0
Receive pin (RX) P2.2 P1.1
RAM stack used 0200h to 021Fh
Working registers R5 to R14
System clock, affected controls BCSCTL1, DCOCTL SCFI0, SCFI1, SCFQCTL
Timer_A, affected controls TACTL, TAR, CCTL0, CCR0
Preparation for software call 
mov.b #00h, &BCSCTL2
mov #00h, SR
br &0C00h
 
mov.b #00h, &FLLCTL1
br    &0C00h
Comment Erase segment command Addresses 1000h to 11FFh are verified coherently (three segments). Also use erase check command.
Table 5-6 BSL Version 2.02 and 2.13 on F21xx, F22xx, F23xx, F24xx, F261x
Device F21xx F22xx F23xx F24x F261x
BSL Version 2.02 2.13
BSL Vector Address Cold Start 0C00h
Warm Start 0C02h(1)
Chip ID Address 0FF0h
Chip ID Data F213h F227h F237h F249h F26Fh
BSL Version Address 0FFAh
BSL Version Data 0202h 0213h
Read and Write Access at 0000h to 00FFh Byte
0100h to FFFEh Word
Verification during write (online) For addresses 0200h to FFFEh
Erase Check Command Yes (error address 0200h)
Erase Segment Command With erasure verification (error address 0200h)
TX Identification command Yes
Change baud rate command Yes
Stack Pointer Initialization Cold Start 0220h 0224h
Warm Start Unchanged
Resources Used by BSL
Transmit Pin (TX) P1.1
Receive Pin (RX) P2.2
RAM Stack Used 0200h to 021Fh 0200h to 0223h
Working Registers R5 to R14 R4 to R15
System clock, affected controls BCSCTL1, DCOCTL SCFI0, SCFI1, SCFQCTL
Timer_A, Affected controls TACTL, TAR, CCTL0, CCR0
Preparation for software call 
mov.b #00h, &BCSCTL2
mov #00h, SR
br &0C00h
Comment Erase Segment Command Addresses 1000h to 11FFh are verified coherently (five segments). Also use erase check command.
(1) The LOCK and LOCKA bits must be cleared by the user application before entering the BSL:
mov.w #FWKEY+LOCKA,&FCTL3
Table 5-7 BSL Version 2.02 and 2.03 on G2xx3, G2xx4, G2xx5, TCH5E(1)
Device G2xx4 G2xx5 G2xx3 TCH5E
BSL Version 2.02 2.03
BSL Vector Address Cold Start 0C00h
Warm Start 0C02h(2)
Chip ID Address 0FF0h
Chip ID Data F227h 2955h 2553h 255Ch
BSL Version Address 0FFAh
BSL Version Data 0202h 0203h
Read and Write Access at 0000h to 00FFh Byte
0100h to FFFEh Word
Verification during write (online) For addresses 0200h to FFFEh
Erase Check Command Yes (error address 0200h)
Erase Segment Command With erasure verification (error address 0200h)
TX Identification command Yes
Change baud rate command Yes
Stack Pointer Initialization Cold Start 0220h
Warm Start Unchanged
Resources Used by BSL
Transmit Pin (TX) P1.1 P1.1
Receive Pin (RX) P2.2 P1.5
RAM Stack Used 0200h to 021Fh
Working Registers R5 to R14
System clock, affected controls BCSCTL1, DCOCTL
Timer_A, Affected controls TACTL, TAR, CCTL0, CCR0
Preparation for software call 
mov.b #00h, &BCSCTL2
mov #00h, SR
br &0C00h
Comment Erase Segment Command Addresses 1000h to 11FFh are verified coherently (five segments). Also use erase check command.
(1) Not all Value Line devices contain a BSL; see device-specific data sheet.
(2) The LOCK and LOCKA bits must be cleared by the user application before entering the BSL:
mov.w #FWKEY+LOCKA,&FCTL3
Table 5-8 BSL Version 2.12 and 2.13 on FG46xx, F471xx
Device FG46xx F471xx
BSL Version 2.12 2.13
BSL vector address Cold start 0C00h
Warm start 0C02h(1)
Chip ID address 0FF0h
Chip ID data F46Fh
BSL version address 0FFAh
BSL version data 0212h 0213h
Mass erase time, nominal (ms) 206.4
Read and write access at 0000h to 00FFh Byte
0100h to FFFEh Word
Verification during write (online) For addresses 0200h to FFFEh
Erase check command Yes (error address 0200h)
Erase segment command Erase segment command with erasure verification (error address 0200h)
TX identification command Yes
Change baud rate command Yes
Stack pointer initialization Cold start 0224h
Warm start Unchanged
Resources Used by BSL
Transmit pin (TX) P1.0
Receive pin (RX) P1.1
RAM stack used 0200h to 0223h
Working registers R4 to R15
System clock, affected controls SCFI0, SCFI1, SCFQCTL
Timer_A, affected controls TACTL, TAR, CCTL0, CCR0
Preparation for software call 
mov.b  #00h, &FLLCTL1
br     &0C00h
Comment Erase segment command Addresses 1000h to 11FFh are verified coherently (five segments). Also use erase check command.
(1) The LOCK and LOCKA bits must be cleared by the user application before entering the BSL:
mov.w #FWKEY+LOCKA,&FCTL3 .