SLAU319AF July   2010  – September 2022

 

  1.   Abstract - MSP430™ Flash Devices Bootloader (BSL)
  2.   Trademarks
  3. 1Introduction
    1. 1.1 Supplementary Online Information
    2. 1.2 Overview of BSL Features
    3. 1.3 BSL Invocation
      1. 1.3.1 Hardware BSL Invocation
        1. 1.3.1.1 MSP430 Devices With Shared JTAG Pins
          1. 1.3.1.1.1 Factors That Prevent BSL Invocation With Shared JTAG Pins
        2. 1.3.1.2 MSP430 Flash Devices With Dedicated JTAG Pins
          1. 1.3.1.2.1 Factors That Prevent BSL Invocation With Dedicated JTAG Pins
        3. 1.3.1.3 Devices With USB
      2. 1.3.2 Software BSL Invocation
    4. 1.4 UART Protocol
    5. 1.5 USB Protocol
  4. 2Bootloader Protocol – 1xx, 2xx, and 4xx Families
    1. 2.1 Synchronization Sequence
    2. 2.2 Commands
      1. 2.2.1 Unprotected Commands
      2. 2.2.2 Password Protected Commands
    3. 2.3 Programming Flow
    4. 2.4 Data Frame
      1. 2.4.1 Data-Stream Structure
      2. 2.4.2 Checksum
      3. 2.4.3 Example Sequence
      4. 2.4.4 Commands – Detailed Description
        1. 2.4.4.1  General
        2. 2.4.4.2  RX Data Block
        3. 2.4.4.3  RX Password
        4. 2.4.4.4  Mass Erase
        5. 2.4.4.5  Erase Segment
        6. 2.4.4.6  Erase Main or Info
        7. 2.4.4.7  Erase Check
        8. 2.4.4.8  Change Baud Rate
        9. 2.4.4.9  Set Memory Offset
        10. 2.4.4.10 Load PC
        11. 2.4.4.11 TX Data Block
        12. 2.4.4.12 TX BSL Version
    5. 2.5 Loadable BSL
    6. 2.6 Exiting the BSL
    7. 2.7 Password Protection
    8. 2.8 Code Protection Fuse
    9. 2.9 BSL Internal Settings and Resources
      1. 2.9.1 Chip Identification and BSL Version
      2. 2.9.2 Vectors to Call the BSL Externally
      3. 2.9.3 Initialization Status
      4. 2.9.4 Memory Allocation and Resources
  5. 3Bootloader Protocol – F5xx and F6xx Families
    1. 3.1 BSL Data Packet
    2. 3.2 UART Peripheral Interface (PI)
      1. 3.2.1 Wrapper
      2. 3.2.2 Abbreviations
      3. 3.2.3 Messages
      4. 3.2.4 Interface Specific Commands
        1. 3.2.4.1 Change Baud Rate
    3. 3.3 I2C Peripheral Interface
      1. 3.3.1 I2C Protocol Definition
      2. 3.3.2 Basic Protocol With Byte Level Acknowledge
      3. 3.3.3 I2C Protocol for BSL - Read From Slave
      4. 3.3.4 Acknowledge (ACK)
      5. 3.3.5 Wrapper
    4. 3.4 USB Peripheral Interface
      1. 3.4.1 Wrapper
      2. 3.4.2 Hardware Requirements
    5. 3.5 BSL Core Command Structure
      1. 3.5.1 Abbreviations
      2. 3.5.2 Command Descriptions
    6. 3.6 BSL Security
      1. 3.6.1 Protected Commands
      2. 3.6.2 RAM Erase
    7. 3.7 BSL Core Responses
      1. 3.7.1 Abbreviations
      2. 3.7.2 BSL Core Messages
      3. 3.7.3 BSL Version Number
      4. 3.7.4 Example Sequences for UART BSL
    8. 3.8 BSL Public Functions and Z-Area
      1. 3.8.1 Starting the BSL From an External Application
      2. 3.8.2 Return to BSL Function Description
  6. 4Bootloader Hardware
    1. 4.1 Hardware Description
      1. 4.1.1 Power Supply
      2. 4.1.2 Serial Interface
        1. 4.1.2.1 Level Shifting
        2. 4.1.2.2 Control of RST/NMI and TEST or TCK Pins
      3. 4.1.3 Target Connector
      4. 4.1.4 Parts List
  7. 5Differences Between Devices and Bootloader Versions
    1. 5.1 1xx, 2xx, and 4xx BSL Versions
    2. 5.2 Special Consideration for ROM BSL Version 1.10
    3. 5.3 1xx, 2xx, and 4xx BSL Known Issues
    4. 5.4 Special Note on the MSP430F14x Device Family BSL
    5. 5.5 F5xx and F6xx Flash-Based BSL Versions
  8. 6Bootloader PCB Layout Suggestion
  9. 7Revision History

2.9.4 Memory Allocation and Resources

  • The BSL program code is located in the boot-ROM area 0C00h to 0FEFh.
  • Addresses 0FF0h to 0FFFh hold the device identification.
  • The BSL variables occupy the RAM area
    • 0200h to 0213h (V1.10)
    • 0200h to 0219h (V1.30 or higher)
  • The BSL stack occupies the RAM area
    • 0214h to 0219h (V1.10)
    • 021Ah to 021Fh (V1.30 or higher, only at cold start)
  • The working registers used are:
    • R5 to R9 (V1.30 or lower) or
    • R5 to R10 (V1.40) or
    • R5 to R11 (V1.60) or
    • R5 to R14 (V2.00 or higher)
    Their contents are not buffered.
    • F1xx and F2xx:
      • The basic clock module registers used are:
        • DCOCTL at address 056h
        • BCSCTL1 at address 057h
    • F4xx:
      • The FLL oscillator and system clock registers used are:
        • SCFI0 at address 050h
        • SCFI1 at address 051h
        • SCFQCTL at address 052h
      • The Timer_A control registers used are:
        • TACTL at address 0160h
        • CCTL0 at address 0162h
        • TAR at address 0170h
        • CCR0 at address 0172h
      • The flash control registers used are:
        • FCTL1 at address 0128h
        • FCTL2 at address 012Ah
        • FCTL3 at address 012Ch
  • No interrupt service is affected.