SLAU319AF July   2010  – September 2022

 

  1.   Abstract - MSP430™ Flash Devices Bootloader (BSL)
  2.   Trademarks
  3. 1Introduction
    1. 1.1 Supplementary Online Information
    2. 1.2 Overview of BSL Features
    3. 1.3 BSL Invocation
      1. 1.3.1 Hardware BSL Invocation
        1. 1.3.1.1 MSP430 Devices With Shared JTAG Pins
          1. 1.3.1.1.1 Factors That Prevent BSL Invocation With Shared JTAG Pins
        2. 1.3.1.2 MSP430 Flash Devices With Dedicated JTAG Pins
          1. 1.3.1.2.1 Factors That Prevent BSL Invocation With Dedicated JTAG Pins
        3. 1.3.1.3 Devices With USB
      2. 1.3.2 Software BSL Invocation
    4. 1.4 UART Protocol
    5. 1.5 USB Protocol
  4. 2Bootloader Protocol – 1xx, 2xx, and 4xx Families
    1. 2.1 Synchronization Sequence
    2. 2.2 Commands
      1. 2.2.1 Unprotected Commands
      2. 2.2.2 Password Protected Commands
    3. 2.3 Programming Flow
    4. 2.4 Data Frame
      1. 2.4.1 Data-Stream Structure
      2. 2.4.2 Checksum
      3. 2.4.3 Example Sequence
      4. 2.4.4 Commands – Detailed Description
        1. 2.4.4.1  General
        2. 2.4.4.2  RX Data Block
        3. 2.4.4.3  RX Password
        4. 2.4.4.4  Mass Erase
        5. 2.4.4.5  Erase Segment
        6. 2.4.4.6  Erase Main or Info
        7. 2.4.4.7  Erase Check
        8. 2.4.4.8  Change Baud Rate
        9. 2.4.4.9  Set Memory Offset
        10. 2.4.4.10 Load PC
        11. 2.4.4.11 TX Data Block
        12. 2.4.4.12 TX BSL Version
    5. 2.5 Loadable BSL
    6. 2.6 Exiting the BSL
    7. 2.7 Password Protection
    8. 2.8 Code Protection Fuse
    9. 2.9 BSL Internal Settings and Resources
      1. 2.9.1 Chip Identification and BSL Version
      2. 2.9.2 Vectors to Call the BSL Externally
      3. 2.9.3 Initialization Status
      4. 2.9.4 Memory Allocation and Resources
  5. 3Bootloader Protocol – F5xx and F6xx Families
    1. 3.1 BSL Data Packet
    2. 3.2 UART Peripheral Interface (PI)
      1. 3.2.1 Wrapper
      2. 3.2.2 Abbreviations
      3. 3.2.3 Messages
      4. 3.2.4 Interface Specific Commands
        1. 3.2.4.1 Change Baud Rate
    3. 3.3 I2C Peripheral Interface
      1. 3.3.1 I2C Protocol Definition
      2. 3.3.2 Basic Protocol With Byte Level Acknowledge
      3. 3.3.3 I2C Protocol for BSL - Read From Slave
      4. 3.3.4 Acknowledge (ACK)
      5. 3.3.5 Wrapper
    4. 3.4 USB Peripheral Interface
      1. 3.4.1 Wrapper
      2. 3.4.2 Hardware Requirements
    5. 3.5 BSL Core Command Structure
      1. 3.5.1 Abbreviations
      2. 3.5.2 Command Descriptions
    6. 3.6 BSL Security
      1. 3.6.1 Protected Commands
      2. 3.6.2 RAM Erase
    7. 3.7 BSL Core Responses
      1. 3.7.1 Abbreviations
      2. 3.7.2 BSL Core Messages
      3. 3.7.3 BSL Version Number
      4. 3.7.4 Example Sequences for UART BSL
    8. 3.8 BSL Public Functions and Z-Area
      1. 3.8.1 Starting the BSL From an External Application
      2. 3.8.2 Return to BSL Function Description
  6. 4Bootloader Hardware
    1. 4.1 Hardware Description
      1. 4.1.1 Power Supply
      2. 4.1.2 Serial Interface
        1. 4.1.2.1 Level Shifting
        2. 4.1.2.2 Control of RST/NMI and TEST or TCK Pins
      3. 4.1.3 Target Connector
      4. 4.1.4 Parts List
  7. 5Differences Between Devices and Bootloader Versions
    1. 5.1 1xx, 2xx, and 4xx BSL Versions
    2. 5.2 Special Consideration for ROM BSL Version 1.10
    3. 5.3 1xx, 2xx, and 4xx BSL Known Issues
    4. 5.4 Special Note on the MSP430F14x Device Family BSL
    5. 5.5 F5xx and F6xx Flash-Based BSL Versions
  8. 6Bootloader PCB Layout Suggestion
  9. 7Revision History

4.1.2.1 Level Shifting

Simple CMOS inverters with Schmitt-trigger characteristics (IC2) are used to transform the RS-232 levels (see Table 4-2) to CMOS levels.

Table 4-2 RS-232 Levels
Logic LevelRS-232 LevelRS-232 Voltage Level
1Mark–3 V to –15 V
0Space3 V to 15 V

The inverters are powered by the operational amplifier IC3A. This amplifier permits adjusting the provided logic level to the requirements of the connected target application. A voltage applied to pin 8 of the BSL target connector (VCC_IN) overrides the default 3-V level provided from IC1 and the 100-kΩ series resistor R11. Thus, the output voltage of the operational amplifier is pulled to the applied voltage VCC_IN.

Depending on the overvoltage protection of the device family selected, the excess voltage is either conducted to VCC (as in the TI 74HC14) or to GND (as in the TI 74AHC14). If the protection diode conducts to VCC, the operational amplifier IC3A needs to compensate for the overvoltage. Therefore, TI recommends the 74AHC14 device, which conducts to ground (GND).

To avoid excessive power dissipation and damage of the protection diodes, series resistors (R1, R2, and R3) are used to limit the input current.

An operational amplifier (IC3B) is used to generate RS-232 levels out of CMOS levels. The level at the positive input is set to VCC/2 (1.5 V nominal). If the level at the negative input rises above this level, the output is pulled to the negative supply of the operational amplifier (mark). If the level drops below VCC/2, the output is pulled to the positive rail (space).

The positive supply of the operational amplifier is the same as the input to the voltage regulator. A separate capacitor (C5) is used to generate the negative supply voltage. This capacitor is charged by the receiving signal of the bootloader hardware (pin 3 on SUB-D connector J2).

During an asynchronous serial communication, the combination of stop bit and start bit is used to synchronize sender and receiver. After the transmission of a data byte, the stop bit forces the transmission line into a defined state, which is usually a logic 1 or, in RS-232 terms, a mark. This means that the transmission-line voltage is negative when there is no transmission and the capacitor can be charged. Diodes are used to prevent discharge of the capacitor during transmission.

In very rare circumstances, the data sent to the bootloader interface might hold too many zeros, so that the capacitor C5 required for the negative supply is discharged, causing a malfunction of the interface. (A possible workaround is to send the data in smaller chunks.) However, under normal operating conditions, even data that contains all zeros does not cause problems.