SLAZ753C October   2025  – November 2025 MSPM0C1103 , MSPM0C1103-Q1 , MSPM0C1104 , MSPM0C1104-Q1

 

  1.   1
  2.   Abstract
  3. 1Functional Advisories
  4. 2Preprogrammed Software Advisories
  5. 3Debug Only Advisories
  6. 4Device Nomenclature
    1. 4.1 Device Symbolization and Revision Identification
  7. 5Advisory Descriptions
    1. 5.1  Fixed by Compiler Advisories
    2. 5.2  ADC_ERR_05
    3. 5.3  CPU_ERR_01
    4. 5.4  CPU_ERR_02
    5. 5.5  CPU_ERR_03
    6. 5.6  FLASH_ERR_04
    7. 5.7  FLASH_ERR_05
    8. 5.8  FLASH_ERR_06
    9. 5.9  FLASH_ERR_08
    10. 5.10 GPIO_ERR_03
    11. 5.11 GPIO_ERR_04
    12. 5.12 I2C_ERR_03
    13. 5.13 I2C_ERR_04
    14. 5.14 I2C_ERR_05
    15. 5.15 I2C_ERR_06
    16. 5.16 I2C_ERR_07
    17. 5.17 I2C_ERR_08
    18. 5.18 I2C_ERR_09
    19. 5.19 I2C_ERR_10
    20. 5.20 I2C_ERR_13
    21. 5.21 RST_ERR_01
    22. 5.22 SPI_ERR_03
    23. 5.23 SPI_ERR_04
    24. 5.24 SPI_ERR_05
    25. 5.25 SPI_ERR_06
    26. 5.26 SPI_ERR_07
    27. 5.27 SYSCTL_ERR_03
    28. 5.28 SYSOSC_ERR_02
    29. 5.29 TIMER_ERR_01
    30. 5.30 TIMER_ERR_04
    31. 5.31 TIMER_ERR_06
    32. 5.32 TIMER_ERR_07
    33. 5.33 UART_ERR_01
    34. 5.34 UART_ERR_02
    35. 5.35 UART_ERR_04
    36. 5.36 UART_ERR_05
    37. 5.37 UART_ERR_06
    38. 5.38 UART_ERR_07
    39. 5.39 UART_ERR_08
    40. 5.40 UART_ERR_09
    41. 5.41 UART_ERR_10
    42. 5.42 UART_ERR_11
  8. 6Revision History

5.26 SPI_ERR_07

SPI Module

Category

Functional

Function

SPI underflow event may not generate if read/write to TXFIFO happen at the same time for SPI peripheral

Description

When SPI.CTL0.SPH = 0 and the device is configured as the SPI peripheral.

If there is a write to the TXFIFO WHILE there is a read request from the SPI controller, then an underflow event may not be generated as the read/write request is happening simultaneously.

Workaround

Ensure the TXFIFO is not empty when the SPI Controller is addressing the device, this can be done by preloading data to avoid a write and read to the same TXFIFO address. Alternatively, data checking strategies, like CRC, can be used to verify the packets were sent properly, then the data can be resent if the CRC doesn't match.