SLAZ753C October 2025 – November 2025 MSPM0C1103 , MSPM0C1103-Q1 , MSPM0C1104 , MSPM0C1104-Q1
UART Module
Functional
Limitation of debug halt feature in UART module
All Tx FIFO elements are sent out before the communication comes to a halt against the expectation of completing the existing frame and halt.
Please make sure data is not written into the TX FIFO after debug halt is asserted.