SLLA640 April   2025 ISO1228

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1ISO1228 - Relevant Device Information
  5. 2Parallel and Serial Output Modes
  6. 3Switching Communication Modes During Operation
    1. 3.1 Parallel to Serial
    2. 3.2 Serial to Parallel
  7. 4SPI Functional Modes
    1. 4.1 Normal Mode
      1. 4.1.1 Normal Mode - Read IN8-IN1 Continuously
    2. 4.2 Burst Mode
  8. 5Maximum Data Throughput in Serial Mode
  9. 6Digital Low Pass Filtering of Outputs
  10. 7Summary
  11. 8References

5 Maximum Data Throughput in Serial Mode

As described in the previous section, ISO1228 can read out two different input packets in a single SPI transaction (one during the address phase and another during the data frame).

The maximum SCLK frequency that ISO1228 supports is 25MHz (when VCC = 2.5V to 5.5V). The maximum data rate of IN8-IN1 that can be read in SPI mode without any loss of information can be calculated using the data sheet timing parameters.

Normal mode - timing parameters Figure 5-1 Normal mode - timing parameters

Given the data sheet specs:

  • TCSCLK = 20ns; the time from nCS low to SCLK first rising edge.
  • TCLKCS = 10ns; the time from SCLK last falling edge to nCS high.

  • TCSW = 250ns; Chip Select High Pulse Width

The time for a single frame (either address or data) can be calculated using Tframe = 8-SCLKbits × Tmin pulse = 8 × 40ns = 320ns, where Tmin pulse = 40ns; Minimum pulse width of SCLK at 25MHz.

The total time for one frame is Total = TCSCLK +TCLKCS + TCSW+ Tframe = 600ns, and the minimum pulse width on INx that can be passed through ISO1228 (Tui) is 660ns. Therefore, there is not any packet loss when reading out input data using SPI.