SLLA640 April   2025 ISO1228

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1ISO1228 - Relevant Device Information
  5. 2Parallel and Serial Output Modes
  6. 3Switching Communication Modes During Operation
    1. 3.1 Parallel to Serial
    2. 3.2 Serial to Parallel
  7. 4SPI Functional Modes
    1. 4.1 Normal Mode
      1. 4.1.1 Normal Mode - Read IN8-IN1 Continuously
    2. 4.2 Burst Mode
  8. 5Maximum Data Throughput in Serial Mode
  9. 6Digital Low Pass Filtering of Outputs
  10. 7Summary
  11. 8References

6 Digital Low Pass Filtering of Outputs

The ISO1228 supports in-built digital low pass filters on the INx and WBx data paths. The filter value for each OUTx channel can be set individually by writing to the addresses indicated in the SPI programmable REGMAP. Alternatively a universal filter for all channels can be set using the F0/F1 device pins (pins 23 and 24). However, the filter setting in the register has the higher priority.

Filtering can be applied to OUTx data as well as wire-break data, however the filters for OUTx are programmable, while the wire-break filter value is fixed and is always ON.

If filtering is enabled (MSB = 1) on any one or more channels in the SPI registers, then register filter settings take priority. If all channels have filters disabled in the register (MSB=0), then F0/F1 takes priority. If F0/F1 = 0/0, then the filters are globally disabled.

The digital low-pass filter averaging time (TFILT) determines the averaging window for the inputs. Filters in ISO1228 are low pass filters and can be set to nine allowed levels.

Table 6-1 Low-Pass Filter Levels
F1 state F0 state Filter Register Setting TFILT Unit
F1=low F0=low 0xxx 0 ns
F1=low F0=float 1000 1 µs
F1=low F0=high 1001 8 µs
F1=float F0=low 1010 200 µs
F1=float F0=float 1011 1 ms
F1=float F0=high 1100 2.5 ms
F1=high F0=low 1101 10 ms
F1=high F0=float 1110 30 ms
F1=high F0=high 1111 100 ms

Each filter is a saturating 3-bit counter with no resets/clears running on an internal clock. The clock period for any filter is the filter delay value divided by 8.

The counter can count the ON duration (value = 1) or OFF duration (value = 0) of each bit in OUTx across packets and assess if the duration surpasses the corresponding filter value. If this does, then only the new value can be stored into the REGMAP and communicated to the MCU. However, unlike a typical glitch filter a pulse shorter than the filter value is not completely rejected. Instead the glitch is attenuated and summed into the signal creating a low-pass response.

The clock period running a filter can be derived as FILTER_TIME/8, for example, in the previous diagram, FILTER_VALUE = 8us, for example, each pulse duration of OUTx has to exceed a min duration of 8us to be communicated to the MCU, and hence FILTER_CLK = 1MHz.

Low Pass Filter Averaging Figure 6-1 Low Pass Filter Averaging

The 3-bit counter can increment every time the counter detects a value = 1 at the filter input and can decrement when the counter detects a value = 0. As shown, the counter has counted up till 6, because the unfiltered OUT1 is 1 for 6us, next on the falling edge of OUT1, the counter decrements to 4, as the input stays low for 2us. All this while the filter output retains the previous value. After this, when OUT1 rises to 1 and stays high for 4 more cycles, the counter reaches value = 8 and the filter output updates to value = 1.