SLLA640 April   2025 ISO1228

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1ISO1228 - Relevant Device Information
  5. 2Parallel and Serial Output Modes
  6. 3Switching Communication Modes During Operation
    1. 3.1 Parallel to Serial
    2. 3.2 Serial to Parallel
  7. 4SPI Functional Modes
    1. 4.1 Normal Mode
      1. 4.1.1 Normal Mode - Read IN8-IN1 Continuously
    2. 4.2 Burst Mode
  8. 5Maximum Data Throughput in Serial Mode
  9. 6Digital Low Pass Filtering of Outputs
  10. 7Summary
  11. 8References

4.1 Normal Mode

In normal SPI mode (BURST_EN = 0), ISO1228 expects 8 bits each of clock (SCLK) and data (SDI) in address phase followed by another 8 bits of SCLK and SDI in the data phase. Figure 4-1 shows the typical timing waveform for a SPI transaction on ISO1228:

SPI Timing in Normal Mode Figure 4-1 SPI Timing in Normal Mode

Due to noise or any other fault, the ISO1228 can become desynchronized from the MCU. For example, the MCU is sending bits for the data phase while ISO1228 is still in the address phase (or vice versa).

To solve this problem, the SYNC pin can be used to synchronize the MCU to ISO1228. The SYNC pin (pin 28) can change states to indicate the current phase of the ISO1228.

  • When SYNC = 1, ISO1228 is in the address frame
  • When SYNC = 0, ISO1228 is in the data frame and sending or receiving data bits

If the MCU detects that the MCU is out of sync with ISO1228, the MCU can read the SYNC pin and then assert low at nRST to clear ISO1228's internal registers and start a new transaction.