SLLA682 July   2025 TDP142

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Device Configuration
  6. 3Equalization Selection
  7. 4Equalization Selection Example
  8. 5AUXP/N and SNOOPENZ Configuration
  9. 6Layout Guidelines
    1. 6.1 GND Stitching
    2. 6.2 AC-Coupling Capacitors
    3. 6.3 Layout Example
  10. 7Summary
  11. 8References

6 Layout Guidelines

The following layout guidelines needs to be used in routing the high-speed DisplayPort signals to and from the TDP142.

  • INDP and OUTDP pairs must be routed with controlled 100Ω differential impedance (±10%).
  • Keep differential pairs away from other high-speed signals.
  • Intra-pair routing needs to be kept to within 5 mils.
  • DisplayPort lane inter-pair routing needs to be kept to within 2 UI according to the DisplayPort Design Guide.
  • Differential pair length matching needs to be near the location of mismatch.
  • Each pair needs to be separated by at least 3 times the signal trace width.
  • The use of bends in differential traces needs to be kept to a minimum. When bends are used, the number of left and right bends needs to be as equal as possible and the angle of the bend needs to be ≥ 135°. This can minimize any length mismatch caused by the bends and minimize the impact bends have on EMI.
  • Route all differential pairs on the same layer.
  • Minimize the number of vias, this is recommended to keep the via count to 2 or less.
  • The layout can face signal crossing on OUTDP2 and OUTDP3 due to mismatched order between the output pins of the device and the connector. One of the designs is to do polarity swap on the input of the device when GPU is BGA package. This can minimize the number of VIAS being used. Please refer to Figure 6-1 and Figure 6-2.
Signal Crossing on the Output Figure 6-1 Signal Crossing on the Output
INDP2 and INDP3 Polarity Swap Figure 6-2 INDP2 and INDP3 Polarity Swap
  • Keep differential traces on layers adjacent to a ground plane.
  • Do not route differential pairs over any split plane.
  • If using a through-hole connector, route the high-speed signals on opposite side of the connector such that the connector pin does not create a stub in the transmission line.
  • Test points needs to be placed in series and in symmetry to avoid impedance discontinuity.