SLLA682 July 2025 TDP142
The TDP142 used in a source/sink application enables the system to pass both transmitter electrical compliance for DisplayPort 1.4 and receiver jitter tolerance compliance testing for DisplayPort 1.4. The TDP142 recovers incoming data from the source and to the sink by applying equalization that compensates for the channel insertion loss. The equalization can be set based on the amount of insertion loss of the channel before the TDP142 receivers (Pre-Channel) and some insertion loss of the channel after the TDP142 (Post-Channel). In the GPIO or pin strap mode, the EQ value of each lane is set globally by configuring the DPEQ[1:0] pins. In the I2C mode, the EQ value of each channel is set independently based on the loss of the individual channel by programming the equivalent registers. The equalization values are detailed in Table 3-1. Typical FR4 trace losses are given in Table 3-2.
| Equalization Setting Number | All DisplayPort Lanes | ||
|---|---|---|---|
| DPEQ1 Pin Level | DPEQ0 Pin Level | EQ GAIN at 4.05GHz (dB) | |
| 0 | 0 | 0 | 1.0 |
| 1 | 0 | R | 3.3 |
| 2 | 0 | F | 4.9 |
| 3 | 0 | 1 | 6.5 |
| 4 | R | 0 | 7.5 |
| 5 | R | R | 8.6 |
| 6 | R | F | 9.5 |
| 7 | R | 1 | 10.4 |
| 8 | F | 0 | 11.1 |
| 9 | F | R | 11.7 |
| 10 | F | F | 12.3 |
| 11 | F | 1 | 12.8 |
| 12 | 1 | 0 | 13.2 |
| 13 | 1 | R | 13.6 |
| 14 | 1 | F | 14.0 |
| 15 | 1 | 1 | 14.4 |
| 4-mil Wide FR4 PCB Trace Length (Inches) | Loss at 2.5GHz (0.49dB/inch) (dB) | Loss at 4.05GHz (0.73dB/inch) (dB) | Loss at 5GHz (0.87dB/inch) (dB) |
|---|---|---|---|
| 1 | 0.5 | 0.7 | 0.9 |
| 2 | 1 | 1.5 | 1.7 |
| 3 | 1.5 | 2.2 | 2.6 |
| 4 | 2 | 2.9 | 3.5 |
| 5 | 2.5 | 3.7 | 4.3 |
| 6 | 2.9 | 4.4 | 5.2 |
| 7 | 3.4 | 5.1 | 6.1 |
| 8 | 3.9 | 5.9 | 7 |
| 9 | 4.4 | 6.6 | 7.8 |
| 10 | 4.9 | 7.3 | 8.7 |