SLLSEY7G June   2017  – February 2025 ISO1211 , ISO1212

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety-Related Certifications
    8. 5.8  Safety Limiting Values
    9. 5.9  Electrical Characteristics—DC Specification
    10. 5.10 Switching Characteristics—AC Specification
    11. 5.11 Insulation Characteristics Curves
    12. 5.12 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Test Circuits
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Sinking Inputs
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Setting Current Limit and Voltage Thresholds
          2. 8.2.1.2.2 Thermal Considerations
          3. 8.2.1.2.3 Designing for 48V Systems
          4. 8.2.1.2.4 Designing for Input Voltages Greater Than 60V
          5. 8.2.1.2.5 Surge, ESD, and EFT Tests
          6. 8.2.1.2.6 Multiplexing the Interface to the Host Controller
          7. 8.2.1.2.7 Status LEDs
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Sourcing Inputs
      3. 8.2.3 Sourcing and Sinking Inputs (Bidirectional Inputs)
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Related Links
    4. 9.4 Receiving Notification of Documentation Updates
    5. 9.5 Support Resources
    6. 9.6 Trademarks
    7. 9.7 Electrostatic Discharge Caution
    8. 9.8 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5.6 Insulation Specifications

PARAMETERTEST CONDITIONSSPECIFICATIONUNIT
D-8DBQ-16
CLRExternal clearance(1)Shortest terminal-to-terminal distance through air43.7mm
CPGExternal Creepage(1)Shortest terminal-to-terminal distance across the package surface43.7mm
DTIDistance through the insulationMinimum internal gap (internal clearance)10.510.5µm
CTIComparative tracking indexDIN EN 60112 (VDE 0303-11); IEC 60112> 600> 600V
Material GroupAccording to IEC 60664-1II
Overvoltage categoryRated mains voltage ≤ 150VRMSI-IVI-IV
Rated mains voltage ≤ 300VRMSI-IIII-III
DIN VDE V 0884-11:2017-01(2)
VIORMMaximum repetitive peak isolation voltageAC voltage (bipolar)566566VPK
VIOWMMaximum working isolation voltageAC voltage (sine wave); time-dependent dielectric breakdown (TDDB) test400400VRMS
DC voltage566566VDC
VIOTMMaximum transient isolation voltageVTEST = VIOTM, t = 60s (qualification),
VTEST = VIOTM, t= 1s (100% production)		36003600VPK
VIOSMMaximum surge isolation voltage(3)Test method per IEC 60065-1, 1.2/50µs waveform,
VTEST = 1.3 × VIOSM = 5200VPK (qualification)		40004000VPK
qpdApparent charge(4)Method a: After I/O safety test subgroup 2/3,
Vini = VIOTM, tini = 60s;
Vpd(m) = 1.2 × VIORM = 680VPK, tm = 10s		< 5< 5pC
Method a: After environmental tests subgroup 1,
Vini = VIOTM, tini = 60s;
Vpd(m) = 1.3 × VIORM = 736VPK, tm = 10s		< 5< 5
Method b1: At routine test (100% production) and preconditioning (type test),
Vini = VIOTM, tini = 1s;
Vpd(m) = 1.5 × VIORM = 849VPK, tm = 10s		< 5< 5
CIOBarrier capacitance, input to output(5)VIO = 0.4 × sin (2 πft), f = 1MHz440560fF
RIOInsulation resistance, input to output(5)VIO = 500V,  TA = 25°C> 1012> 1012Ω
VIO = 500V,  100°C ≤ TA ≤ 125°C> 1011> 1011
VIO = 500V at  TS = 150°C> 109> 109
Pollution degree22
Climatic category40/125/2140/125/21
UL 1577
VISOWithstand isolation voltageVTEST = VISO = 2500VRMS, t = 60s (qualification);
VTEST = 1.2 × VISO = 3000VRMS, t = 1s (100% production)		25002500VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.
(2) This coupler is suitable for basic electrical insulation only within the maximum operating ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-terminal device