SLLSF86D May   2018  – August 2026 ISOW1412 , ISOW1432

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Supply Current Characteristics at VISOOUT = 3.3 V
    11. 6.11 Supply Current Characteristics at  VISOOUT = 5 V
    12. 6.12 Switching Characteristics at VISOOUT = 3.3 V
    13. 6.13 Switching Characteristics at VISOOUT = 5 V
    14. 6.14 Insulation Characteristics Curves
    15. 6.15 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Power Isolation
    3. 8.3 Signal Isolation
    4. 8.4 RS-485
    5. 8.5 Functional Block Diagram
    6. 8.6 Feature Description
      1. 8.6.1 Power-Up and Power-Down Behavior
      2. 8.6.2 Protection Features
      3. 8.6.3 Failsafe Receiver
      4. 8.6.4 Glitch-Free Power Up and Power Down
    7. 8.7 Device Functional Modes
    8. 8.8 Device I/O Schematics
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Data Rate, Bus Length and Bus Loading
        2. 9.2.2.2 Stub Length
      3. 9.2.3 Insulation Lifetime
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

8.6.1 Power-Up and Power-Down Behavior

The ISOW14x2 family of devices has built-in under-voltage lockout (UVLO) on all supplies (VDD, VIO and VISOOUT) with positive-going and negative-going thresholds and hysteresis. Both the power converter supply (VDD) and Logic supply (VIO) need to be present for the device to work. If either of them is below UVLO, both the signal path and the power converter are disabled.

Assuming VIO is above UVLO+, when the VDD voltage crosses the positive-going UVLO threshold during power-up, the DC-DC converter initializes and the power converter duty cycle is increased in a controlled manner. This soft-start scheme limits primary peak currents drawn from the VDD supply and charges the VISOOUT output in a controlled manner, avoiding overshoots. RS-485 driver output is in high impedance state in this duration. When the UVLO positive-going threshold is crossed on the secondary side VISOOUT pin, the feedback channel starts providing feedback to the primary controller. The regulation loop takes over and RS-485 drive output, Received data output (R) and general purpose logic output (OUT) take the respective states defined by the inputs to the device, the Driver enable (DE), driver data to be transmitted (D), Receiver enable (RE) and general purpose logic input (IN) respectively. Designers must consider a sufficient time margin (typically 5ms with 10µF load capacitance) to allow this power up sequence before any usable system functionality.

When either of VDD or VIO is lost, the primary side DC-DC controller turns off when the UVLO lower threshold is reached. The VISOOUT capacitor then discharges depending on the isolation channels and RS-485 load.