SLLSF86D May   2018  – August 2026 ISOW1412 , ISOW1432

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Supply Current Characteristics at VISOOUT = 3.3 V
    11. 6.11 Supply Current Characteristics at  VISOOUT = 5 V
    12. 6.12 Switching Characteristics at VISOOUT = 3.3 V
    13. 6.13 Switching Characteristics at VISOOUT = 5 V
    14. 6.14 Insulation Characteristics Curves
    15. 6.15 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Power Isolation
    3. 8.3 Signal Isolation
    4. 8.4 RS-485
    5. 8.5 Functional Block Diagram
    6. 8.6 Feature Description
      1. 8.6.1 Power-Up and Power-Down Behavior
      2. 8.6.2 Protection Features
      3. 8.6.3 Failsafe Receiver
      4. 8.6.4 Glitch-Free Power Up and Power Down
    7. 8.7 Device Functional Modes
    8. 8.8 Device I/O Schematics
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Data Rate, Bus Length and Bus Loading
        2. 9.2.2.2 Stub Length
      3. 9.2.3 Insulation Lifetime
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

6.6 Insulation Specifications

PARAMETER TEST CONDITIONS VALUE UNIT
GENERAL
CLR External clearance(1) Shortest terminal-to-terminal distance through air >8 mm
CPG External creepage(1) Shortest terminal-to-terminal distance across the package surface >8 mm
DTI Distance through the insulation Minimum internal gap (internal clearance – capacitive signal isolation) >17 µm
Minimum internal gap (internal clearance- transformer power isolation) >120
CTI Comparative tracking index DIN EN 60112 (VDE 0303-11); IEC 60112 >600 V
Material group According to IEC 60664-1 I
Overvoltage category per IEC 60664-1 Rated mains voltage ≤ 150VRMS I-IV
Rated mains voltage ≤ 300VRMS I-IV
Rated mains voltage ≤ 600VRMS I-IV
Rated mains voltage ≤ 1000VRMS I-III
DIN EN IEC 60747-17 (VDE 0884-17)(2)
VIORM Maximum repetitive peak isolation voltage AC voltage (bipolar) 1500 VPK
VIOWM Maximum working isolation voltage AC voltage (sine wave) Time dependent dielectric breakdown (TDDB) test 1000 VRMS
DC voltage 1500 VDC
VIOTM Maximum transient isolation voltage VTEST = VIOTM, t = 60s (qualification);
VTEST = 1.2 × VIOTM, t = 1s (100% production)		 7071 VPK
VIOSM Maximum surge isolation voltage ISOW14x2(3) Test method per IEC 62368-1, 1.2/50µs waveform 10000 VPK
VIOSM Maximum surge isolation voltage ISOW14x2B(3) Test method per IEC 62368-1, 1.2/50µs waveform 7800 VPK
qpd Apparent charge(4) Method a: After I/O safety test subgroup 2/3,
Vini = VIOTM, tini = 60s;
Vpd(m) = 1.2 × VIORM , tm = 10s		 ≤5 pC
Method a: After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s;
ISOW14x2: Vpd(m) = 1.6 × VIORM , tm = 10s
ISOW14x2B: Vpd(m) = 1.2 × VIORM , tm = 10s		 ≤5
Method b1: At routine test (100% production)
Vini = 1.2 × VIOTM, tini = 1s;
ISOW14x2: Vpd(m) = 1.875 × VIORM , tm = 1s (method b1)
ISOW14x2B: Vpd(m) = 1.5 × VIORM , tm = 1s (method b1), or
Vpd(m) = Vini, tm = tini (method b2)		 ≤5
CIO Barrier capacitance, input to output(5) VIO = 0.4 sin (2πft), f = 1MHz ≅3.5 pF
RIO Isolation resistance, input to output(5) VIO = 500V, TA = 25°C >1012 Ω
VIO = 500V, 100°C ≤ TA ≤ 125°C >1011 Ω
VIO = 500V at TS = 150°C >109 Ω
Pollution degree 2
Climatic category 40/125/21
UL 1577
VISO Withstand isolation voltage VTEST = VISO = 5000VRMS, t = 60s (qualification);
VTEST = 1.2 × VISO = 6000VRMS, t = 1s (100% production)		 5000 VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.
(2) ISOW14x2 is suitable for safe electrical insulation and ISOW14x2B is suitable for basic electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-terminal device