SLLSFE3A December   2021  – March 2026 TCAN1164-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configurations and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 ESD Ratings IEC Specification
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Power Supply Characteristics
    7. 6.7 Electrical Characteristics
    8. 6.8 Switching Characteristics
    9. 6.9 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  VSUP Pin
      2. 8.3.2  VCCOUT Pin
      3. 8.3.3  Digital Inputs and Outputs
      4. 8.3.4  GND
      5. 8.3.5  nRST Pin
      6. 8.3.6  SDO
      7. 8.3.7  nCS Pin
      8. 8.3.8  SCLK
      9. 8.3.9  SDI
      10. 8.3.10 CAN Bus Pins
      11. 8.3.11 Local Faults
        1. 8.3.11.1 TXD Dominant Timeout (TXD DTO)
        2. 8.3.11.2 Thermal Shutdown (TSD)
        3. 8.3.11.3 Under/Over Voltage Lockout
        4. 8.3.11.4 Unpowered Devices
        5. 8.3.11.5 Floating Terminals
        6. 8.3.11.6 CAN Bus Short Circuit Current Limiting
        7. 8.3.11.7 Sleep Wake Error Timer
      12. 8.3.12 Watchdog
        1. 8.3.12.1 Watchdog Error Counter
        2. 8.3.12.2 Watchdog SPI Control Programming
        3. 8.3.12.3 Watchdog Timing
        4. 8.3.12.4 Question and Answer Watchdog
          1. 8.3.12.4.1 WD Question and Answer Basic information
          2. 8.3.12.4.2 Question and Answer Register and Settings
          3. 8.3.12.4.3 WD Question and Answer Value Generation
        5. 8.3.12.5 Question and Answer WD Example
          1. 8.3.12.5.1 Example configuration for desired behavior
          2. 8.3.12.5.2 Example of performing a question and answer sequence
      13. 8.3.13 Bus Fault Detection and Communication
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operating Mode Description
        1. 8.4.1.1 Normal Mode
        2. 8.4.1.2 Silent Mode
        3. 8.4.1.3 Standby Mode
          1. 8.4.1.3.1 Wake-Up Pattern (WUP) Detection in Standby Mode
        4. 8.4.1.4 Reset Mode
        5. 8.4.1.5 Fail-safe Mode
      2. 8.4.2 CAN Transceiver
        1. 8.4.2.1 CAN Transceiver Operation
        2. 8.4.2.2 CAN Transceiver Modes
          1. 8.4.2.2.1 CAN Off Mode
          2. 8.4.2.2.2 CAN Autonomous: Inactive and Active
          3. 8.4.2.2.3 CAN Active
        3. 8.4.2.3 Driver and Receiver Function Tables
        4. 8.4.2.4 CAN Bus States
    5. 8.5 Programming
      1. 8.5.1 Serial Peripheral Interface (SPI) Communication
      2. 8.5.2 Serial Clock Input (SCLK)
      3. 8.5.3 Serial Data Input (SDI)
      4. 8.5.4 Serial Data Output (SDO)
      5. 8.5.5 Chip Select Not (nCS)
      6. 8.5.6 Registers
        1. 8.5.6.1  DEVICE_ID_y Register (Address = 0h + formula) [reset = xxh]
        2. 8.5.6.2  REV_ID_MAJOR Register (Address = 8h) [reset = 00h]
        3. 8.5.6.3  REV_ID_MINOR Register (Address = 9h) [reset = 00h]
        4. 8.5.6.4  SPI_RSVD_x Register (Address = Ah + formula) [reset = 00h]
        5. 8.5.6.5  Scratch_Pad_SPI Register (Address = Fh) [reset = 00h]
        6. 8.5.6.6  MODE_CNTRL Register (Address = 10h) [reset = 04h]
        7. 8.5.6.7  WD_CONFIG_1 Register (Address = 13h) [reset = 54h]
        8. 8.5.6.8  WD_CONFIG_2 Register (Address = 14h) [reset = 02h]
        9. 8.5.6.9  WD_INPUT_TRIG Register (Address = 15h) [reset = 00h]
        10. 8.5.6.10 WD_QA_CONFIG Register (Address = 2Dh) [reset = 0h]
        11. 8.5.6.11 WD_QA_ANSWER Register (Address = 2Eh) [reset = 0h]
        12. 8.5.6.12 WD_QA_QUESTION Register (Address = 2Fh) [reset = 0h]
        13. 8.5.6.13 STATUS (address = 40h) [reset = 00h]
        14. 8.5.6.14 INT_GLOBAL Register (Address = 50h) [reset = 0h]
        15. 8.5.6.15 INT_1 Register (Address = 51h) [reset = 0h]
        16. 8.5.6.16 INT_2 Register (Address = 52h) [reset = 40h]
        17. 8.5.6.17 INT_3 Register (Address 53h) [reset = 0h]
        18. 8.5.6.18 INT_CANBUS Register (Address = 54h) [reset = 0h]
        19. 8.5.6.19 INT_ENABLE_1 Register (Address = 56h) [reset = F3h]
        20. 8.5.6.20 INT_ENABLE_2 Register (Address = 57h) [reset = 3Fh]
        21. 8.5.6.21 INT_ENABLE_3 Register (Address =58h) [reset = 80h]
        22. 8.5.6.22 INT_ENABLE_CANBUS Register (Address = 59h) [reset = 7Fh]
        23. 8.5.6.23 INT_RSVD_y Register (Address = 5Ah + formula) [reset = 00h]
  10. 9 Application Information Disclaimer
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Bus Loading, Length and Number of Nodes
      2. 9.2.2 Detailed Design Procedures
        1. 9.2.2.1 CAN Termination
    3. 9.3 Application Curves
    4. 9.4 Power Supply Requirements
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

8.3.8 SCLK

The SCLK pin is the SPI clock. The clock rate should not exceed the max fSCK value.