SLLSFO6 Data sheet

SLLSFO6A May 2024 – December 2025 TCAN2410-Q1 , TCAN2411-Q1

PRODUCTION DATA

9.1 Device Registers

Table 9-1 lists the memory-mapped registers for the Device registers. All register offset addresses not listed in Table 9-1 should be considered as reserved locations and the register contents should not be modified.

Table 9-1 DEVICE Registers

Address	Acronym	Register Name	Section
0h	DEVICE_ID_241x	Device Part Number	Section 9.1.1
8h	REV_ID	Major and Minor Revision	Section 9.1.2
9h	SPI_CONFIG	SPI mode configuration	Section 9.1.3
Ah	CRC_CNTL	SPI CRC control	Section 9.1.4
Bh	CRC_POLY_SET	Sets SPI CRC polynomial	Section 9.1.5
Ch	SBC_CONFIG	SBC, HSS and VCC2 select	Section 9.1.6
Dh	VREG_CONFIG1	Configures VCC1 regulator	Section 9.1.7
Eh	SBC_CONFIG1	SBC Configuration	Section 9.1.8
Fh	Scratch_Pad_SPI	Read and Write Test Register SPI	Section 9.1.9
10h	CAN_CNTRL_1	CAN transceiver 1 control	Section 9.1.10
11h	WAKE_PIN_CONFIG1	WAKE pin configuration 1	Section 9.1.11
12h	WAKE_PIN_CONFIG2	WAKE pin configuration 2	Section 9.1.12
13h	WD_CONFIG_1	Watchdog configuration 1	Section 9.1.13
14h	WD_CONFIG_2	Watchdog configuration 2	Section 9.1.14
15h	WD_INPUT_TRIG	Watchdog input trigger	Section 9.1.15
16h	WD_RST_PULSE	Watchdog output pulse width	Section 9.1.16
17h	FSM_CONFIG	Fail safe mode configuration	Section 9.1.17
18h	FSM_CNTR	Fail safe mode counter	Section 9.1.18
19h	DEVICE_CONFIG0	Device reset configuration	Section 9.1.19
1Ah	DEVICE_CONFIG1	Device configuration 1	Section 9.1.20
1Bh	DEVICE_CONFIG2	Device configuration 2	Section 9.1.21
1Ch	SWE_TIMER	Sleep wake error timer configuration	Section 9.1.22
1Eh	HSS_CNTL	High side switch 1 and 2 control	Section 9.1.23
1Fh	PWM1_CNTL1	Pulse width modulation frequency configuration	Section 9.1.24
20h	PWM1_CNTL2	Pulse width modulation duty cycle two MSB select	Section 9.1.25
21h	PWM1_CNTL3	Pulse width modulation duty cycle eight LSB select	Section 9.1.26
22h	PWM2_CNTL1	Pulse width modulation 2 frequency selection	Section 9.1.27
23h	PWM2_CNTL2	Pulse width modulation duty cycle two MSB select	Section 9.1.28
24h	PWM2_CNTL3	Pulse width modulation duty cycle eight LSB select	Section 9.1.29
25h	TIMER1_CONFIG	High side switch timer 1 configuration	Section 9.1.30
26h	TIMER2_CONFIG	High side switch timer 2 configuration	Section 9.1.31
28h	RSRT_CNTR	Restart counter configuration	Section 9.1.32
29h	nRST_GFO_CNTL	nRST and GFO pin control	Section 9.1.33
2Ah	WAKE_PIN_CONFIG3	Multiple wake input configuration and reporting for WAKE pin	Section 9.1.34
2Bh	WAKE_PIN_CONFIG4		Section 9.1.35
2Dh	WD_QA_CONFIG	Question and Answer Watchdog Configuration	Section 9.1.36
2Eh	WD_QA_ANSWR	Register for writing answer to the QA watchdog	Section 9.1.37
2Fh	WD_QA_QUESTION	QA watchdog question value and error count setting	Section 9.1.38
30h	SW_ID1	Selective wake ID1 register	Section 9.1.39
31h	SW_ID2	Selective wake ID2 register	Section 9.1.40
32h	SW_ID3	Selective wake ID3 register	Section 9.1.41
33h	SW_ID4	Selective wake ID4 register	Section 9.1.42
34h	SW_ID_MASK1	Selective wake ID MASK1 register	Section 9.1.43
35h	SW_ID_MASK2	Selective wake ID MASK2 register	Section 9.1.44
36h	SW_ID_MASK3	Selective wake ID MASK3 register	Section 9.1.45
37h	SW_ID_MASK4	Selective wake ID MASK4 register	Section 9.1.46
38h	SW_ID_MASK_DLC	Selective wake ID MASK DLC register	Section 9.1.47
39h	DATA0	Selective wake DATA0	Section 9.1.48
3Ah	DATA1	Selective wake DATA1	Section 9.1.49
3Bh	DATA2	Selective wake DATA2	Section 9.1.50
3Ch	DATA3	Selective wake DATA3	Section 9.1.51
3Dh	DATA4	Selective wake DATA4	Section 9.1.52
3Eh	DATA5	Selective wake DATA5	Section 9.1.53
3Fh	DATA6	Selective wake DATA6	Section 9.1.54
40h	DATA7	Selective wake DATA7	Section 9.1.55
44h	SW_CONFIG_1	Selective wake config register1	Section 9.1.56
45h	SW_CONFIG_2	Selective wake config register2	Section 9.1.57
46h	SW_CONFIG_3	Selective wake config register3	Section 9.1.58
47h	SW_CONFIG_4	Selective wake config register4	Section 9.1.59
4Dh	HSS_CNTL2	HSS3 and 4 Control register	Section 9.1.60
4Eh	EEPROM	Customer EEPROM programming register	Section 9.1.61
4Fh	HSS_CNTL3	VHSS OV/UV, Control for Cyclic wake in Sleep mode	Section 9.1.62
50h	INT_GLOBAL	Global interrupt register	Section 9.1.63
51h	INT_1	Includes CAN, LWU, SW pin wake interrupts	Section 9.1.64
52h	INT_2	Includes UVCC1, OVCC1, UVSUP interrupts	Section 9.1.65
53h	INT_3	INT3 register	Section 9.1.66
54h	INT_CANBUS_1	CAN BUS fault interrupts	Section 9.1.67
55h	INT_7	HSS OC and OL interrupts	Section 9.1.68
56h	INT_EN_1	Enable for INT1	Section 9.1.69
57h	INT_EN_2	Enable for INT2	Section 9.1.70
58h	INT_EN_3	Enable for INT3	Section 9.1.71
59h	INT_EN_CANBUS_1	Enable for INT_CANBUS	Section 9.1.72
5Ah	INT_4	INT4 register	Section 9.1.73
5Ch	INT_6	INT6 register	Section 9.1.74
5Eh	INT_EN_4	Enable for INT4	Section 9.1.75
60h	INT_EN_6	Enable for INT6	Section 9.1.76
62h	INT_EN_7	Enable for INT7	Section 9.1.77
65h	BUCK_CONFIG1	BUCK regulator configuration register	Section 9.1.78
78h	ID_PIN_STATUS	ID Pin Status register	Section 9.1.79
79h	WAKE_ID_CONFIG1	ID1 and ID2 configuration	Section 9.1.80
7Ah	WAKE_ID_CONFIG2	ID3 and ID4 configuration	Section 9.1.81
7Bh	WAKE_PIN_CONFIG5	WKAE4 pin configuration	Section 9.1.82

Complex bit access types are encoded to fit into small table cells. Table 9-2 shows the codes that are used for access types in this section.

Table 9-2 Device Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
RH	R H	Read Set or cleared by hardware
Write Type
W	W	Write
W0C	W 0C	Write 0 to clear
W1C	W 1C	Write 1 to clear
Reset or Default Value
-n		Value after reset or the default value

9.1.1 DEVICE_ID_241x Register (Address = 0h) [Reset = 00h]

DEVICE_ID_241x is shown in Table 9-3.

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Device part number. Offset = 0h + y; where y = 0h to 7h

Table 9-3 DEVICE_ID_241x Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	DEVICE_ID	R	00000000b	The DEVICE_ID[1:8] registers determine the part number of the device. The reset values and value of each DEVICE_ID register are listed for the corresponding register address Address 00h = 43h = C Address 01h = 32h = 2 Address 02h = 34h = 4 Address 03h = 31h = 1 Address 04h = 30h = 0 for TCAN2410-Q1 Address 04h = 31h = 1 for TCAN2411-Q1 Address 05h - 07h = RSVD

9.1.2 REV_ID Register (Address = 8h) [Reset = 2Xh]

REV_ID is shown in Table 9-4.

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Table 9-4 REV_ID Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	Major_Revision	RH	0010b	Major die revision. Reset value indicates the major die revision (full layer revisions) 0001b = 1 0010b = 2
3-0	Minor_Revision	RH	xxxxb	Minor die revision. Reset value indicates the minor die revision (metal layer revisions) 0000b = 0 0001b = 1

9.1.3 SPI_CONFIG Register (Address = 9h) [Reset = 00h]

SPI_CONFIG is shown in Table 9-5.

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Table 9-5 SPI_CONFIG Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RESERVED	R	0b	Reserved
3	BYTE_CNT	R/W	0b	Selects the data byte count for a read or write operation. Note that for two byte configuration, SPI CRC is not available 0b = One byte 1b = Two byte
2	SDI_POL	R/W	0b	Selects the idle polarity of the SDI input pin by configuring the internal pull-up or pull-down resistor configuration 0b = Pull-down 1b = Pull-up
1-0	SPI_MODE	R/W	00b	Configures the SPI mode 00b = Mode 0 (CPOL is 0, CPHA is 0) 01b = Mode 1 (CPOL is 0, CPHA is 1) 10b = Mode 2 (CPOL is 1, CPHA is 0) 11b = Mode 3 (CPOL is 1, CPHA is 1)

9.1.4 CRC_CNTL Register (Address = Ah) [Reset = 00h]

CRC_CNTL is shown in Table 9-6.

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Table 9-6 CRC_CNTL Register Field Descriptions

Bit	Field	Type	Reset	Description
7-1	RESERVED	R	0b	Reserved
0	CRC_EN	R/W	0b	Enables SPI CRC 0b = Disable 1b = Enable

9.1.5 CRC_POLY_SET Register (Address = Bh) [Reset = 00h]

CRC_POLY_SET is shown in Table 9-7.

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Table 9-7 CRC_POLY_SET Register Field Descriptions

Bit	Field	Type	Reset	Description
7-1	RESERVED	R	0b	Reserved
0	POLY_8_SET	R/W	0b	Sets the 8-bit polynomial for CRC. 0b = X^8 + X^5 + X^3 + X^2 + X + 1 (0x2F) 1b = X^8 + X^4 + X^3 + X^2 + 1 (0x1D SAE J1850)

9.1.6 SBC_CONFIG Register (Address = Ch) [Reset = 86h]

SBC_CONFIG is shown in Table 9-8.

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Table 9-8 SBC_CONFIG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	VCC1_OV_SEL	R/W	1b	OVCC1 threshold selection bit 0b = Lower threshold 1b = Higher threshold
6	OVCC1_ACTION	R/W	0b	Configuring the SBC action due to OVCC1 0b = Enter fail-safe mode 1b = Only set OVCC1 interrupt and do not enter fail-safe mode
5	PWM_SEL	R/W	0b	Determines which PWM is selected for programming 0b = PWM1 and PWM2 1b = PWM3 and PWM4
4	VCC1_SNK_DIS	R/W	0b	Enables/Disables VCC1 sink current 0b = VCC1 sink enabled (default) 1b = VCC1 sink disabled
3-2	SBC_MODE_SEL	RH/W	01b	Determines the mode that the SBC is in. Can be set by the controller. These bits also updated by hardware e.g. when waking up from Sleep to Standby mode or fail-safe to Standby mode 00b = Sleep 01b = Standby 10b = Normal 11b = Reserved
1-0	VCC2_CFG	R/W	10b	VCC2 voltage regulator configuration 00b = VCC2 off in all SBC modes 01b = VCC2 on in all SBC modes except Failsafe 10b = VCC2 on in all SBC modes except Sleep and Failsafe 11b = Reserved

9.1.7 VREG_CONFIG1 Register (Address = Dh) [Reset = A0h]

VREG_CONFIG1 is shown in Table 9-9.

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Table 9-9 VREG_CONFIG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	VCC1_CFG	R/W	10b	VCC1 voltage regulator configuration 00b = Reserved 01b = On in all SBC modes except Fail-safe mode 10b = On in all SBC modes except Sleep and Fail-safe modes 11b = Reserved
5	FPWM_OVSUP_DIS	R/W	1b	Disable FPWM on OVSUP to reduce ringing on VCC1 output at High VSUP values. If selected, the buck regulator automatically switches to PFM mode 0b = Do not disable FPWM on OVSUP 1b = Disable FPWM on OVSUP
4	RESERVED	R	0b	Reserved
3	VCC1_SINK	R/W	0b	VCC1 current sink strength selection 0b = 10 µA 1b = 1000 µA
2-0	RESERVED	R	0b	Reserved

9.1.8 SBC_CONFIG1 Register (Address = Eh) [Reset = 01h]

SBC_CONFIG1 is shown in Table 9-10.

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Table 9-10 SBC_CONFIG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	CAN_SLOPE_CTRL_EN	R/W	0b	TCAN241x: CAN transceiver slope control enable 0b = Disabled 1b = Enabled
6	FSM_CYC_WK_EN	R/W	0b	Enables cyclic wake in fail-safe mode 0b = Disabled 1b = Enabled
5	VCC1_SLP_ACT	R/W	0b	Action to take when VCC1 is enabled on in sleep mode due to a wake event 0b = Indicate wake event with nINT pin only, device remains in Sleep mode 1b = Transition to Standby mode via Restart mode
4-3	UVCC1_SEL	R/W	00b	VCC1 under-voltage threshold selection 00b = Threshold 1 01b = Threshold 2 10b = Threshold 3 11b = Threshold 4
2	SW_FSM_EN	R/W	0b	Enables the SW pin to become a digital wake up pin when in Fail-safe mode 0b = Disabled 1b = Enabled
1	SW_SLP_EN	R/W	0b	Enables the SW pin to become a digital wake up pin when in Sleep mode 0b = Disabled 1b = Enabled
0	SW_POL_SEL	R/W	1b	SW pin polarity select 0b = Active low 1b = Active high

9.1.9 Scratch_Pad_SPI Register (Address = Fh) [Reset = 00h]

Scratch_Pad_SPI is shown in Table 9-11.

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Table 9-11 Scratch_Pad_SPI Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	Scratch_Pad	R/W	00000000b	Read and Write Test Pad for SPI

9.1.10 CAN_CNTRL_1 Register (Address = 10h) [Reset = 04h]

CAN_CNTRL_1 is shown in Table 9-12.

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Table 9-12 CAN_CNTRL_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	SW_EN	R/W	0b	Selective wake enable 0b = Disabled 1b = Enabled
6	TXD_DTO_DIS	R/W	0b	CAN TXD Dominant time out disable control 0b = Enabled 1b = Disabled
5	FD_EN	R/W	0b	Bus fault diagnostic enable 0b = Disabled 1b = Enabled
4	RESERVED	R	0b	Reserved
3	CAN1_FSM_DIS	R/W	0b	Sets the CAN transceiver operating state when device enters FSM 0b = Wake capable 1b = Off
2-0	CAN1_TRX_SEL	R/W	100b	CAN transceiver control 000b = Off 001b = Reserved 010b = SBC Mode Control WUP disabled 011b = Reserved 100b = Wake capable 101b = Listen 110b = SBC Mode Control 111b = On

9.1.11 WAKE_PIN_CONFIG1 Register (Address = 11h) [Reset = 00h]

WAKE_PIN_CONFIG1 is shown in Table 9-13.

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Table 9-13 WAKE_PIN_CONFIG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	WAKE_CONFIG	R/W	00b	Wake pin configuration: Note: Pulse requires more programming 00b = Bi-directional - either edge 01b = Rising edge 10b = Falling edge 11b = Pulse
5	WAKE1_STAT	RH	0b	Provides status of WAKE1 pin. 0b = Low 1b = High
4	RESERVED	R	0b	Reserved
3-2	WAKE_PULSE_INVALID	R/W	00b	Pulses less than or equal to these pulses are considered invalid 00b = 5 ms and sets tWAKE_WIDTH_MIN to 10 ms 01b = 10 ms and sets tWAKE_WIDTH_MIN to 20 ms 10b = 20 ms and sets tWAKE_WIDTH_MIN to 40 ms 11b = 40 ms and sets tWAKE_WIDTH_MIN to 80 ms
1-0	WAKE_PULSE_MAX	R/W	00b	Maximum WAKE pin input pulse width to be considered valid. 00b = 750 ms 01b = 1000 ms 10b = 1500 ms 11b = 2000 ms

9.1.12 WAKE_PIN_CONFIG2 Register (Address = 12h) [Reset = 02h]

WAKE_PIN_CONFIG2 is shown in Table 9-14.

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Table 9-14 WAKE_PIN_CONFIG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	WAKE_PULSE_CONFIG	R/W	0b	Sets the expected pulse direction for all wake pins 0b = Low->High->Low 1b = High->Low->High
6	WAKE1_SENSE	R/W	0b	WAKE1 pin configured for static or cyclic sensing wake 0b = Static Sensing 1b = Cyclic Sensing
5	TWK_CYC_SET	R/W	0b	Sets the tWK_CYC time (µs) for determining WAKE pin status for cyclic sensing for all WAKE pins 0b = 35 us 1b = 100 us
4-3	nINT_SEL	R/W	00b	nINT configuration selection 00b = Global interrupt 01b = Watchdog failure output 10b = Bus fault interrupt 11b = Wake request
2	RXD_WK_CONFIG	R/W	0b	Configures RXD pin behavior from a wake event 0b = Pulled low 1b = Toggle
1-0	WAKE1_LEVEL	R/W	10b	Sets the WAKE1 pin input thresholds 00b = VCC1 01b = 2.5V 10b = 4V 11b = 6V

9.1.13 WD_CONFIG_1 Register (Address = 13h) [Reset = 82h]

WD_CONFIG_1 is shown in Table 9-15.

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Table 9-15 WD_CONFIG_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	WD_CONFIG	R/W	10b	Watchdog configuration 00b = Disabled 01b = Timeout 10b = Window 11b = Q&A
5-4	WD_PRE	R/W	00b	Watchdog pre-scalar 00b = Factor 1 01b = Factor 2 10b = Factor 3 11b = Factor 4
3	WD_SLP_EN	R/W	0b	Enables watchdog in Sleep mode 0b = watchdog disabled in Sleep mode 1b = watchdog enabled in Sleep mode
2	WD_STBY_TYPE	R/W	0b	Selects the watchdog type in Standby mode if enabled 0b = Timeout 1b = Matches the watchdog type in Normal mode
1-0	WD_LW_SEL	R/W	10b	Selects the long window duration in Standby mode. 00b = 150 ms 01b = 300 ms 10b = 600 ms (default) 11b = 1000 ms

9.1.14 WD_CONFIG_2 Register (Address = 14h) [Reset = 60h]

WD_CONFIG_2 is shown in Table 9-16.

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Table 9-16 WD_CONFIG_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-5	WD_TIMER	R/W	011b	Sets window or timeout times based upon the WD_PRE setting, See WD_TIMER table
4-1	WD_ERR_CNT	RH	0000b	Watchdog error counter. Provides the running count of watchdog errors up to WD_ERR_CNT_SET threshold
0	WD_STBY_DIS	R/W	0b	Disables the watchdog in standby mode. 0b = Enabled 1b = Disabled

9.1.15 WD_INPUT_TRIG Register (Address = 15h) [Reset = 00h]

WD_INPUT_TRIG is shown in Table 9-17.

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Table 9-17 WD_INPUT_TRIG Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	WD_INPUT	R/W1C	00000000b	Write FFh to trigger WD at appropriate time

9.1.16 WD_RST_PULSE Register (Address = 16h) [Reset = 00h]

WD_RST_PULSE is shown in Table 9-18.

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Table 9-18 WD_RST_PULSE Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	WD_ERR_CNT_SET	R/W	0000b	Sets the watchdog event error counter threshold. The device will enter Restart mode and assert LIMP upon overflow
3-0	RSRT_CNTR	R/W1C	0000b	Provides the number of times the device has entered restart mode and should be cleared prior to reaching the RSRT_CNTR_SEL value

9.1.17 FSM_CONFIG Register (Address = 17h) [Reset = 00h]

FSM_CONFIG is shown in Table 9-19.

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Table 9-19 FSM_CONFIG Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	FSM_CNTR_ACT	R/W	0000b	Action if fail safe counter exceeds programmed value 0000b = Disabled 0001b = Reserved 0010b = Reserved 0011b = Perform hard reset - POR 0100b = Stop responding to wake events and go to sleep until power cycle reset
3-1	FSM_SLP_STAT	RH	000b	Reason for entering fail-safe or sleep mode 000b = Status Clear 001b = Thermal shut down event 010b = Reserved 011b = VCC1 fault 100b = Reserved 101b = SWE Timer (Sleep Mode) 110b = Reserved 111b = Restart counter exceeded These values are held until cleared by writing oh to FSM_CNTR_STAT
0	FSM_DIS	R/W	0b	Fail safe mode disable 0b = Enabled 1b = Disabled

9.1.18 FSM_CNTR Register (Address = 18h) [Reset = 00h]

FSM_CNTR is shown in Table 9-20.

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Table 9-20 FSM_CNTR Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	FSM_CNTR_SET	R/W	0000b	Sets the number of times FS mode enters before action taken per FSM_CNTR_ACT. 0000b = 1 0001b = 1 0010b = 2 0011b = 3 0100b = 4 0101b = 5 0110b = 6 0111b = 7 1000b = 8 1001b = 9 1010b = 10 1011b = 11 1100b = 12 1101b = 13 1110b = 14 1111b = 15
3-0	FSM_CNTR_STAT	RH/W0C	0000b	Reads back the number of time FSM has been entered in a row up to 15. Can be cleared by writing 0h.

9.1.19 DEVICE_CONFIG0 Register (Address = 19h) [Reset = 20h]

DEVICE_CONFIG0 is shown in Table 9-21.

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Table 9-21 DEVICE_CONFIG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	NVM_REV	R	0010b	Internal NVM revision
3-2	RESERVED	R	0b	Reserved
1	SF_RST	R/W1C	0b	Soft Reset: Writing a 1 causes a soft reset. Device registers return to default values while keeping the regulators on.
0	HD_RST	R/W1C	0b	Hard Reset: Forces a power on reset on writing a 1. This will set the PWRON interrupt flag

9.1.20 DEVICE_CONFIG1 Register (Address = 1Ah) [Reset = 00h]

DEVICE_CONFIG1 is shown in Table 9-22.

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Table 9-22 DEVICE_CONFIG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	LIMP_SLP_FLT_EN	R/W	0b	Turn on LIMP in Sleep mode for TSD and VCC1 faults (in addition to watchdog fault) 0b = Disabled 1b = Enabled
6-5	RESERVED	R	0b	Reserved
4	LIMP_DIS	R/W	0b	Configures the LIMP function 0b = Enabled 1b = Disabled
3-2	LIMP_SEL_RESET	R/W	00b	Selects the method to reset/turn off LIMP 00b = On third successful input trigger the error counter receives 01b = First correct input trigger 10b = Reserved 11b = Reserved
1	LIMP_RESET	R/W1C	0b	LIMP reset. Writing 1b to this bit resets the LIMP pin and bit is cleared automatically. Note: If the fault causing the LIMP pin to go active is not cleared, the LIMP pin will be set to active again.
0	FSM_CYC_SEN_EN	R/W	0b	Enables cyclic sensing wake up for fail-safe mode 0b = Disabled 1b = Enabled

9.1.21 DEVICE_CONFIG2 Register (Address = 1Bh) [Reset = 00h]

DEVICE_CONFIG2 is shown in Table 9-23.

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Table 9-23 DEVICE_CONFIG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	LIMP_LSS_SEL	R/W	00b	Selects LIMP pin function. Note: This register field reads back 00b if 8'h1A[4]=0b (LIMP functionality is enabled) 00b = LIMP 01b = Low side switch 10b = Reserved 11b = Reserved
5-3	LIMP_LSS_CNTL	R/W	000b	Selects the output of LSS at the LIMP pin 000b = Off 001b = PWM1 010b = PWM2 011b = Timer1 100b = Timer2 101b = On 110b = PWM3 111b = PWM4
2	VSUP_UVLO_SEL	R/W	0b	Selects the UVLO level on VSUP at which the buck regulator is turned off 0b = Lower UVLO Level (Typ 3.2V) 1b = Higher UVLO Level (Typ 5 V)
1	WAKE_WIDTH_MAX_DIS	R/W	0b	Disables the Max limit, tWK_PULSE_WIDTH_MAX detection when pulse is selected for WAKE pin configuration. 0b = Enabled 1b = Disabled
0	RESERVED	R	0b	Reserved

9.1.22 SWE_TIMER Register (Address = 1Ch) [Reset = 28h]

SWE_TIMER is shown in Table 9-24.

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Table 9-24 SWE_TIMER Register Field Descriptions

Bit	Field	Type	Reset	Description
7	SWE_EN	R/W	0b	Sleep wake error enable: NOTE: This enables the SWE timer when coming out of sleep mode on a wake event. If this is enabled a SPI read or write must take place within this four minute window or the device returns to sleep. This does not disable the function for initial power on or in case of a power on reset. 0b = Disabled 1b = Enabled
6-3	SWE_TIMER_SET	R/W	0101b	Sets the timer used for tINACTIVE in minutes 0000b = 2 0001b = 2.5 0010b = 3 0011b = 3.5 0100b = 4 0101b = 4.5 0110b = 5 0111b = 5.5 1000b = 6 1001b = 6.5 1010b = 8 1011b = 8.5 1100b = 10
2	CANSLNT_SWE_DIS	R/W	0b	Disables the SWE timer connection with the CANSLNT flag. 0b = Enabled 1b = Disabled
1-0	RESERVED	R	0b	Reserved

9.1.23 HSS_CNTL Register (Address = 1Eh) [Reset = 00h]

HSS_CNTL is shown in Table 9-25.

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Table 9-25 HSS_CNTL Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0b	Reserved
6-4	HSS1_CNTL	R/W	000b	Control for high side switch 1 000b = Off 001b = PWM1 010b = PWM2 011b = Timer1 100b = Timer2 101b = On 110b = PWM3 111b = PWM4
3	RESERVED	R	0b	Reserved
2-0	HSS2_CNTL	R/W	000b	Control for high side switch 2 000b = Off 001b = PWM1 010b = PWM2 011b = Timer1 100b = Timer2 101b = On 110b = PWM3 111b = PWM4

9.1.24 PWM1_CNTL1 Register (Address = 1Fh) [Reset = 00h]

PWM1_CNTL1 is shown in Table 9-26.

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Table 9-26 PWM1_CNTL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	PWM1_FREQ	R/W	0b	Selects PWM1 frequency (Hz) 0b = 200 1b = 400
6-0	RESERVED	R	0b	Reserved

9.1.25 PWM1_CNTL2 Register (Address = 20h) [Reset = 00h]

PWM1_CNTL2 is shown in Table 9-27.

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Table 9-27 PWM1_CNTL2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-2	RESERVED	R	0b	Reserved
1-0	PWM1_DC_MSB	R/W	00b	Most significant two bits for 10-bit PWM1 duty cycle select. Works with 'h21[7:0] Note: When configuring HSS3 it is best to align PWM3 if PWM is to be used. PWM1 control will change to PWM3 when register 8'hC[5] = 0b. 00b = 100% off when used with 'h21[7:0] 11b = 100% on when used with h21[7:0]

9.1.26 PWM1_CNTL3 Register (Address = 21h) [Reset = 00h]

PWM1_CNTL3 is shown in Table 9-28.

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Table 9-28 PWM1_CNTL3 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	PWM1_DC	R/W	00000000b	Bits 7-0 for 10-bit PWM1 duty cycle select. Works with 'h20[1:0] to provide a resolution of 1/1023 Note: When configuring HSS3 it is best to align PWM3 if PWM is to be used. PWM1 control will change to PWM3 when register 8'hC[5] = 0b. 00000000b = 100% off when used with 'h20[1:0] 11111111b = 100% on when used with 'h20[1:0]

9.1.27 PWM2_CNTL1 Register (Address = 22h) [Reset = 00h]

PWM2_CNTL1 is shown in Table 9-29.

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Table 9-29 PWM2_CNTL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	PWM2_FREQ	R/W	0b	Selects PWM2 frequency (Hz) 0b = 200 1b = 400
6-0	RESERVED	R	0b	Reserved

9.1.28 PWM2_CNTL2 Register (Address = 23h) [Reset = 00h]

PWM2_CNTL2 is shown in Table 9-30.

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Table 9-30 PWM2_CNTL2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-2	RESERVED	R	0b	Reserved
1-0	PWM2_DC_MSB	R/W	00b	Most significant two bits for 10-bit PWM2 duty cycle select. Works with 'h24[7:0] Note: When configuring HSS4 it is best to align PWM4 if PWM is to be used. PWM2 control will change to PWM4 when register 8'hC[5] = 0b. 00b = 100% off when used with 'h24[7:0] 11b = 100% on when used with 'h24[7:0]

9.1.29 PWM2_CNTL3 Register (Address = 24h) [Reset = 00h]

PWM2_CNTL3 is shown in Table 9-31.

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Table 9-31 PWM2_CNTL3 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	PWM2_DC	R/W	00000000b	Bits 7-0 for 10-bit PWM2 duty cycle select. Works with 'h23[1:0] to provide a resolution of 1/1023 Note: When configuring HSS4 it is best to align PWM4 if PWM is to be used. PWM2 control will change to PWM4 when register 8'hC[5] = 0b. 00000000b = 100% off when used with 'h23[1:0] 11111111b = 100% on when used with 'h23[1:0]

9.1.30 TIMER1_CONFIG Register (Address = 25h) [Reset = 00h]

TIMER1_CONFIG is shown in Table 9-32.

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Table 9-32 TIMER1_CONFIG Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	TIMER1_ON_WIDTH	R/W	0000b	Sets the high side switch on time (ms) for timer 1 0000b = Off (HSS is high impedance) 0001b = 0.1 0010b = 0.3 0011b = 0.5 0100b = 1 0101b = 10 0110b = 20 0111b = 30 1000b = 40 1001b = 50 1010b = 60 1011b = 80 1100b = 100 1101b = 150 1110b = 200 1111b = On (HSS is on 100%)
3	TIMER1_CYC_WK_EN	R/W	0b	Enables Cyclic Wake using Timer 1 0b = Disabled 1b = Enabled
2-0	TIMER1_PERIOD	R/W	000b	Sets the timer period (ms) for timer 1 000b = 10 001b = 20 010b = 50 011b = 100 100b = 200 101b = 500 110b = 1000 111b = 2000

9.1.31 TIMER2_CONFIG Register (Address = 26h) [Reset = 00h]

TIMER2_CONFIG is shown in Table 9-33.

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Table 9-33 TIMER2_CONFIG Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	TIMER2_ON_WIDTH	R/W	0000b	Sets the high side switch on time (ms) for timer 2 0000b = Off (HSS is high impedance) 0001b = 0.1 0010b = 0.3 0011b = 0.5 0100b = 1 0101b = 10 0110b = 20 0111b = 30 1000b = 40 1001b = 50 1010b = 60 1011b = 80 1100b = 100 1101b = 150 1110b = 200 1111b = On (HSS is on 100%)
3	TIMER2_CYC_WK_EN	R/W	0b	Enables Cyclic Wake using Timer 2 0b = Disabled 1b = Enabled
2-0	TIMER2_PERIOD	R/W	000b	Sets the timer period (ms) for timer 2 000b = 10 001b = 20 010b = 50 011b = 100 100b = 200 101b = 500 110b = 1000 111b = 2000

9.1.32 RSRT_CNTR Register (Address = 28h) [Reset = 40h]

RSRT_CNTR is shown in Table 9-34.

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Table 9-34 RSRT_CNTR Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RSRT_CNTR_SEL	R/W	0100b	Selects the number of times the device can enter restart mode prior to device entering sleep mode, 0 to 15 times. Note: Writing 0h here disables the restart counter.
3-0	RESERVED	R	0b	Reserved

9.1.33 nRST_GFO_CNTL Register (Address = 29h) [Reset = 0Ch]

nRST_GFO_CNTL is shown in Table 9-35.

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Table 9-35 nRST_GFO_CNTL Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R	0b	Reserved
5	nRST_PULSE_WIDTH	R/W	0b	Sets the pulse width for nRST when the device enters restart mode due to WD failure or nRST release delay after VCC1 clears UVCC1 threshold 0b = 2 ms 1b = 15 ms
4	GFO_POL_SEL	R/W	0b	Selects the polarity for the GFO pin Note: When 8'h29[3:1] = 110b, this bit determines the state of the GFO output 0b = Active low 1b = Active high
3-1	GFO_SEL	R/W	110b	Selects the information that will cause this pin to be pulled to the state selected by 'h29[4] for tNRST_TOG except for when general purpose output is selected 000b = VCC1/2 interrupt (overvoltage, undervoltage or short) 001b = WD interrupt event (each one) 010b = Reserved 011b = Local wake request (LWU) 100b = Bus wake request (WUP) 101b = Restart counter exceeded (indicated in standby mode) 110b = General purpose output 111b = CAN Bus fault
0	RESERVED	R	0b	Reserved

9.1.34 WAKE_PIN_CONFIG3 Register (Address = 2Ah) [Reset = F0h]

WAKE_PIN_CONFIG3 is shown in Table 9-36.

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Table 9-36 WAKE_PIN_CONFIG3 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	WAKE4_PIN_SET	R/W	1b	Configures whether WAKE4 is active or inactive 0b = WAKE4 inactive 1b = WAKE4 active
6	WAKE3_PIN_SET	R/W	1b	Configures whether WAKE3 is active or inactive 0b = WAKE3 inactive 1b = WAKE3 active
5	WAKE2_PIN_SET	R/W	1b	Configures whether WAKE2 is active or inactive 0b = WAKE2 inactive 1b = WAKE2 active
4	WAKE1_PIN_SET	R/W	1b	Configures whether WAKE1 is active or inactive 0b = WAKE1 inactive 1b = WAKE1 active
3-0	MULTI_WAKE_STAT	R/W0C	0000b	Provides which WAKE input state has changed based upon specific bits. Bits represent WAKE input so if multiple WAKE input bits are set indicates that those specific WAKE inputs cause the WAKE event. 0001b = Wake 1 0010b = Wake 2 0100b = Wake 3 1000b = Wake 4

9.1.35 WAKE_PIN_CONFIG4 Register (Address = 2Bh) [Reset = 22h]

WAKE_PIN_CONFIG4 is shown in Table 9-37.

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Table 9-37 WAKE_PIN_CONFIG4 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	WAKE2_SENSE	R/W	0b	WAKE2 pin configured for static or cyclic sensing wake 0b = Static sensing 1b = Cyclic sensing
6	WAKE2_STAT	RH	0b	Provides status of WAKE2 pin. 0b = Low 1b = High
5-4	WAKE2_LEVEL	R/W	10b	Sets the WAKE2 pin input thresholds 00b = VCC1 01b = 2.5V 10b = 4V 11b = 6V
3	WAKE3_SENSE	R/W	0b	WAKE3 pin configured for static or cyclic sensing wake 0b = Static sensing 1b = Cyclic sensing
2	WAKE3_STAT	RH	0b	Provides status of WAKE3 pin. 0b = Low 1b = High
1-0	WAKE3_LEVEL	R/W	10b	Sets the WAKE3 pin input thresholds 00b = VCC1 01b = 2.5V 10b = 4V 11b = 6V

9.1.36 WD_QA_CONFIG Register (Address = 2Dh) [Reset = 0Ah]

WD_QA_CONFIG is shown in Table 9-38.

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Table 9-38 WD_QA_CONFIG Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	WD_ANSW_GEN_CFG	R/W	00b	WD answer generation configuration
5-4	WD_QA_POLY_CFG	R/W	00b	WD Q&A polynomial configuration
3-0	WD_QA_POLY_SEED	R/W	1010b	WD Q&A polynomial seed value loaded when device is in the RESET state

9.1.37 WD_QA_ANSWR Register (Address = 2Eh) [Reset = 00h]

WD_QA_ANSWR is shown in Table 9-39.

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Table 9-39 WD_QA_ANSWR Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	WD_QA_ANSWER	R/W1C	00000000b	MCU Q&A Watchdog answer

9.1.38 WD_QA_QUESTION Register (Address = 2Fh) [Reset = 3Ch]

WD_QA_QUESTION is shown in Table 9-40.

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Table 9-40 WD_QA_QUESTION Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0b	Reserved
6	QA_ERROR	R/W1C	0b	Watchdog Q&A answer error flag
5-4	WD_ANSW_CNT	RH	11b	Current state of received watchdog Q&A error counter
3-0	WD_QUESTION	RH	1100b	Current watchdog question value

9.1.39 SW_ID1 Register (Address = 30h) [Reset = 00h]

SW_ID1 is shown in Table 9-41.

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Table 9-41 SW_ID1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	EXT_ID_17:10	R/W	00000000b	Extended ID bits 17:10

9.1.40 SW_ID2 Register (Address = 31h) [Reset = 00h]

SW_ID2 is shown in Table 9-42.

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Table 9-42 SW_ID2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	EXT_ID_9:2	R/W	00000000b	Extended ID bits 9:2

9.1.41 SW_ID3 Register (Address = 32h) [Reset = 00h]

SW_ID3 is shown in Table 9-43.

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Table 9-43 SW_ID3 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	EXT_ID_1:0	R/W	00b	Extended ID bits 1:0
5	IDE	R/W	0b	Extended ID field 0b = Standard ID (11-bits) 1b = Extended ID (29-bits)
4-0	ID_10:6__EXT_ID_28:24	R/W	00000b	ID[10:6] and Extended ID[28:24]

9.1.42 SW_ID4 Register (Address = 33h) [Reset = 00h]

SW_ID4 is shown in Table 9-44.

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Table 9-44 SW_ID4 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-2	ID_5:0__EXT_ID_23:18	R/W	000000b	ID[5:0] and Extended ID[23:18]
1-0	RESERVED	R	0b	Reserved

9.1.43 SW_ID_MASK1 Register (Address = 34h) [Reset = 00h]

SW_ID_MASK1 is shown in Table 9-45.

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Table 9-45 SW_ID_MASK1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-2	RESERVED	R	0b	Reserved
1-0	EXT_ID_MASK_17:16	R/W	00b	Extended ID Mask 17:16

9.1.44 SW_ID_MASK2 Register (Address = 35h) [Reset = 00h]

SW_ID_MASK2 is shown in Table 9-46.

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Table 9-46 SW_ID_MASK2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	EXT_ID_MASK_15:8	R/W	00000000b	Extended ID Mask 15:8

9.1.45 SW_ID_MASK3 Register (Address = 36h) [Reset = 00h]

SW_ID_MASK3 is shown in Table 9-47.

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Table 9-47 SW_ID_MASK3 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	EXT_ID_MASK_7:0	R/W	00000000b	Extended ID Mask 7:0

9.1.46 SW_ID_MASK4 Register (Address = 37h) [Reset = 00h]

SW_ID_MASK4 is shown in Table 9-48.

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Table 9-48 SW_ID_MASK4 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	ID_MASK_10:3__EXT_ID_MASK_28:21	R/W	00000000b	ID Mask 10:3 and Extended ID Mask 28:21 (Base ID)

9.1.47 SW_ID_MASK_DLC Register (Address = 38h) [Reset = 00h]

SW_ID_MASK_DLC is shown in Table 9-49.

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Table 9-49 SW_ID_MASK_DLC Register Field Descriptions

Bit	Field	Type	Reset	Description
7-5	ID_MASK_2:0__EXT_ID_MASK_20:18	R/W	000b	ID Mask 2:0 and Extended ID Mask 20:18 (Base ID)
4-1	DLC	R/W	0000b	DLC[3:0]
0	DATA_MASK_EN	R/W	0b	Data mask enable 0b = DLC field and Data field are not compared and assumed valid. Remote frames are allowed. 1b = DLC field must match DLC[3:0] register and data field bytes are compared with DATAx registers for a matching 1. Remote frames are ignored

9.1.48 DATA0 Register (Address = 39h) [Reset = 00h]

DATA0 is shown in Table 9-50.

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Table 9-50 DATA0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	DATA0	R/W	00000000b	CAN data byte 0

9.1.49 DATA1 Register (Address = 3Ah) [Reset = 00h]

DATA1 is shown in Table 9-51.

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Table 9-51 DATA1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	DATA1	R/W	00000000b	CAN data byte 1

9.1.50 DATA2 Register (Address = 3Bh) [Reset = 00h]

DATA2 is shown in Table 9-52.

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Table 9-52 DATA2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	DATA2	R/W	00000000b	CAN data byte 2

9.1.51 DATA3 Register (Address = 3Ch) [Reset = 00h]

DATA3 is shown in Table 9-53.

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Table 9-53 DATA3 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	DATA3	R/W	00000000b	CAN data byte 3

9.1.52 DATA4 Register (Address = 3Dh) [Reset = 00h]

DATA4 is shown in Table 9-54.

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Table 9-54 DATA4 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	DATA4	R/W	00000000b	CAN data byte 4

9.1.53 DATA5 Register (Address = 3Eh) [Reset = 00h]

DATA5 is shown in Table 9-55.

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Table 9-55 DATA5 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	DATA5	R/W	00000000b	CAN data byte 5

9.1.54 DATA6 Register (Address = 3Fh) [Reset = 00h]

DATA6 is shown in Table 9-56.

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Table 9-56 DATA6 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	DATA6	R/W	00000000b	CAN data byte 6

9.1.55 DATA7 Register (Address = 40h) [Reset = 00h]

DATA7 is shown in Table 9-57.

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Table 9-57 DATA7 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	DATA7	R/W	00000000b	CAN data byte 7

9.1.56 SW_CONFIG_1 Register (Address = 44h) [Reset = 50h]

SW_CONFIG_1 is shown in Table 9-58.

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Table 9-58 SW_CONFIG_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	SW_FD_PASSIVE	R/W	0b	Selective Wake FD Passive: this bit modifies the behavior of the error counter when CAN with flexible data rate frames are seen. 0b = CAN with flexible data rate frame will be counted as an error frame 1b = CAN with flexible data rate frame are ignored (passive)
6-4	CAN_DR	R/W	101b	CAN bus data rate 000b = 50 Kbps 001b = 100 Kbps 010b = 125 Kbps 011b = 250 Kbps 100b = Reserved 101b = 500 Kbps 110b = Reserved 111b = 1 Mbps
3-2	FD_DR	R/W	00b	CAN bus FD data rate 00b = CAN FD ≤ 4x CAN data rate 01b = CAN FD ≥ 5x and ≤ 10x CAN data rate 10b = CAN FD 8 Mbps versus 500k CAN data rate 11b = Reserved
1-0	RESERVED	R	0b	Reserved

9.1.57 SW_CONFIG_2 Register (Address = 45h) [Reset = 00h]

SW_CONFIG_2 is shown in Table 9-59.

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Table 9-59 SW_CONFIG_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	FRAME_CNTx	RH	00000000b	Frame Error Counter: this error counter is incremented by 1 for every received frame error detected (stuff bit, CRC or CRC delimiter form error). The counter is decremented by 1 for every correctly received CAN frame assuming the counter is not zero. In case the device is set for passive on CAN with flexible data rate frames, any frame detected as a CAN FD frame will have no impact on the frame error counter (no increment or decrement). If the frame counter reaches FRAME_CNT_THRESHOLD[7:0] value the next increment will overflow the counter, set FRAME_OVF flag. The counter is reset by the following: enabling the frame detection or tSILENCE detection.

9.1.58 SW_CONFIG_3 Register (Address = 46h) [Reset = 1Fh]

SW_CONFIG_3 is shown in Table 9-60.

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Table 9-60 SW_CONFIG_3 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	FRAME_CNT_THRESHOLD	R/W	00011111b	Frame Error Counter Threshold: these bits set the point at which the error counter reaches its maximum and on the next error frame will overflow and set the FRAME_OVF flag. Default is 31 so the 32nd error will set the overflow flag.

9.1.59 SW_CONFIG_4 Register (Address = 47h) [Reset = 00h]

SW_CONFIG_4 is shown in Table 9-61.

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Table 9-61 SW_CONFIG_4 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	SWCFG	R/W	0b	Selective wake configuration complete. Note: Writing to any of these wake configuration registers (8'h30-8'h44, 8'h46) clears the SWCFG bit. 0b = SW registers not configured or received a FRAME_OVF fault. 1b = SW registers configured Note: Make this the last step in configuring and turning on selective wake.
6	CAN_SYNC_FD	RH	0b	device is properly decoding CAN FD frames if frame detection is enabled. This flag, is updated after every received frame. By polling this flag the system may determine if the device is properly decoding CAN FD frames, up to but not including the Data Field. This flag is self-clearing.
5	CAN_SYNC	RH	0b	Synchronized to CAN data: this flag indicates the device is properly decoding CAN frames if frame detection is enabled. This flag is updated after every received frame. By polling this flag, the system may determine if the device is properly decoding CAN frames. This flag is self-clearing.
4-0	RESERVED	R	0b	Reserved

9.1.60 HSS_CNTL2 Register (Address = 4Dh) [Reset = 00h]

HSS_CNTL2 is shown in Table 9-62.

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Table 9-62 HSS_CNTL2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0b	Reserved
6-4	HSS3_CNTL	R/W	000b	Control for high side switch 3 000b = Off 001b = PWM1 010b = PWM2 011b = Timer1 100b = Timer2 101b = On 110b = PWM3 111b = PWM4
3	RESERVED	R	0b	Reserved
2-0	HSS4_CNTL	R/W	000b	Control for high side switch 4 000b = Off 001b = PWM1 010b = PWM2 011b = Timer1 100b = Timer2 101b = On 110b = PWM3 111b = PWM4

9.1.61 EEPROM Register (Address = 4Eh) [Reset = 00h]

EEPROM is shown in Table 9-63.

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Table 9-63 EEPROM Register Field Descriptions

Bit	Field	Type	Reset	Description
7	EEPROM_SAVE	R/W	0b	Saves configuration bits to EEPROM. Write a 1b and correct code to register 8'h4E[3:0] to save configuration bits to EEPROM. Self clears after EEPROM is written to.
6	EEPROM_CRC_CHK	R/W	0b	Force EEPROM CRC check 0b = Do not read or check CRC 1b = Force read and CRC check
5	EEPROM_RELOAD	R/W	0b	Forces memory to be reloaded from EEPROM 0b = Don not reload 1b = Reload EEPROM
4	RESERVED	R	0b	Reserved
3-0	EEPROM_CODE	R/W	0000b	Code to access EERPOM is Ah. Automatically clears back to 0h

9.1.62 HSS_CNTL3 Register (Address = 4Fh) [Reset = 00h]

HSS_CNTL3 is shown in Table 9-64.

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Table 9-64 HSS_CNTL3 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	HSS_OV_SD_DIS	R/W	0b	Configures HSS shut-down due to OVHSS 0b = HSS are shut-off due to OVHSS 1b = HSS remain ON even during OVHSS
6	HSS_UV_SD_DIS	R/W	0b	Configures HSS shut-down due to UVHSS 0b = HSS are shut-off due to UVHSS 1b = HSS remain ON even during UVHSS
5	HSS_OV_UV_REC	R/W	0b	Configures the auto-recovery of the high-side switches when turned off due to an OVHSS or UVHSS event 0b = Enabled (auto-recovers HSS outputs when OV/UVHSS event is cleared) 1b = Disabled (auto-recovery disabled. Controller has to manually turn the HSS back on after the OV/UVHSS event is cleared)
4	SLP_CYC_WK_EN	R/W	0b	Enables cyclic wake when in sleep mode based upon timer1 or timer2 0b = Disabled 1b = Enabled
3	RESERVED	R	0b	Reserved
2	VCC2_STATUS	RH	0b	VCC2 LDO status 0b = UVCC2 or off 1b = In regulation
1	VCAN_STATUS	RH	0b	VCAN LDO status 0b = UVCAN or off 1b = In regulation
0	RSTRT_TIMER_SEL	R/W	0b	Selects the restart timer used to exit restart mode if VCC1 does not exceed UVCC1R 0b = tRSTTO 1b = tINACTIVE

9.1.63 INT_GLOBAL Register (Address = 50h) [Reset = 00h]

INT_GLOBAL is shown in Table 9-65.

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Table 9-65 INT_GLOBAL Register Field Descriptions

Bit	Field	Type	Reset	Description
7	INT_7	RH	0b	Logical OR of INT_7
6	INT_1	RH	0b	Logical OR of INT_1
5	INT_2	RH	0b	Logical OR of INT_2
4	INT_3	RH	0b	Logical OR of INT_3
3	INT_CANBUS	RH	0b	Logical OR of INT_CANBUS register
2	INT_4	RH	0b	Logical OR of INT_4
1	RESERVED	R	0b	Reserved
0	INT_6	RH	0b	Logical OR of INT_6

9.1.64 INT_1 Register (Address = 51h) [Reset = 00h]

INT_1 is shown in Table 9-66.

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Table 9-66 INT_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	WD	R/W1C	0b	Watchdog event interrupt. NOTE: This interrupt bit will be set for every watchdog error event and does not rely upon the Watchdog error counter
6	CANINT_1	R/W1C	0b	CAN bus wake up interrupt
5	LWU	R/W1C	0b	Local wake up
4	WKERR	R/W1C	0b	Wake error bit is set when the SWE timer has expired and the state machine has returned to Sleep mode
3	FRAME_OVF_1	R/W1C	0b	Frame error counter overflow
2	CANSLNT_1	R/W1C	0b	CAN bus inactive for tSILENCE
1	SWPIN_WU	R/W1C	0b	SW pin wake up interrupt
0	CANDOM_1	R/W1C	0b	CAN bus stuck dominant

9.1.65 INT_2 Register (Address = 52h) [Reset = 40h]

INT_2 is shown in Table 9-67.

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Table 9-67 INT_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	SMS	R/W1C	0b	Sleep mode status flag. Only sets when sleep mode is entered by a WKERR, UVIO timeout or UVIO + TSD fault
6	PWRON	R/W1C	1b	Power on
5	OVCC1	R/W1C	0b	VCC1 overvoltage
4	UVSUP5	R/W1C	0b	UVSUP5 undervoltage
3	UVSUP3	R/W1C	0b	UVSUP3 undervoltage
2	UVCC1	R/W1C	0b	VCC1 undervoltage
1	TSD_SBC	R/W1C	0b	SBC Thermal Shutdown due to VCC1 Or HSS (interrupt indicated after recovering from fail-safe mode)
0	SME	R/W1C	0b	Sleep Mode Exit interrupt when device is in sleep mode, VCC1 is on and exited to restart or fail-safe mode due to a VCC1 fault or watchdog fault if enabled

9.1.66 INT_3 Register (Address = 53h) [Reset = 00h]

INT_3 is shown in Table 9-68.

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Table 9-68 INT_3 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	SPIERR	R/W1C	0b	Sets when SPI status bit sets
6	SWERR	RH	0b	Logic OR of (SWE_EN and NOT (SWCFG)) and FRAME_OVF Selective wake may not be enabled while SWERR is set
5	FSM	R/W1C	0b	Entered fail-safe mode. Can be cleared while in FSM
4	CRCERR	R/W1C	0b	SPI transaction CRC error detected
3	VCC1SC	R/W1C	0b	VCC1 short detected
2	RSRT_CNT	R/W1C	0b	Restart counter exceeded programmed count
1	TSD_CAN	R/W1C	0b	Thermal Shutdown due to VCC2 or CAN
0	CRC_EEPROM	R/W1C	0b	EEPROM CRC error

9.1.67 INT_CANBUS_1 Register (Address = 54h) [Reset = 00h]

INT_CANBUS_1 is shown in Table 9-69.

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Table 9-69 INT_CANBUS_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	UVCAN	R/W1C	0b	UVCAN interrupt
6	RESERVED	R	0b	Reserved
5	CANHCANL	R/W1C	0b	CANH and CANL shorted together
4	CANHBAT	R/W1C	0b	CANH shorted to Vbat
3	CANLGND	R/W1C	0b	CANL shorted to GND
2	CANBUSOPEN	R/W1C	0b	CAN bus open
1	CANBUSGND	R/W1C	0b	CAN bus shorted to GND or CANH shorted to GND
0	CANBUSBAT	R/W1C	0b	CAN bus shorted to Vbat or CANL shorted to Vbat

9.1.68 INT_7 Register (Address = 55h) [Reset = 00h]

INT_7 is shown in Table 9-70.

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Table 9-70 INT_7 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	HSSOC1	R/W1C	0b	High side switch 1 over current
6	HSSOL1	R/W1C	0b	High side switch 1 open load
5	HSSOC2	R/W1C	0b	High side switch 2 over current
4	HSSOL2	R/W1C	0b	High side switch 2 open load
3	HSSOC3	R/W1C	0b	High side switch 3 over current
2	HSSOL3	R/W1C	0b	High side switch 3 open load
1	HSSOC4	R/W1C	0b	High side switch 4 over current
0	HSSOL4	R/W1C	0b	High side switch 4 open load

9.1.69 INT_EN_1 Register (Address = 56h) [Reset = FFh]

INT_EN_1 is shown in Table 9-71.

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Table 9-71 INT_EN_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	WD_EN	R/W	1b	Watchdog event detected mask
6	CANINT_EN	R/W	1b	CAN bus wake up interrupt mask
5	LWU_EN	R/W	1b	Local wake up mask
4	WKERR_EN	R/W	1b	Wake error mask
3	FRAME_OVF_EN	R/W	1b	Frame error counter overflow mask
2	CANSLNT_EN	R/W	1b	CAN silent mask
1	SWPIN_WU_EN	R/W	1b	SW pin wake up interrupt mask
0	CANDOM_EN	R/W	1b	CAN bus stuck dominant mask

9.1.70 INT_EN_2 Register (Address = 57h) [Reset = 7Fh]

INT_EN_2 is shown in Table 9-72.

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Table 9-72 INT_EN_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	SMS_EN	R	0b	SMS flag enable (read-only)
6	PWRON_EN	R	1b	Power on flag enable (not changeable)
5	OVCC1_EN	R/W	1b	VCC1 overvoltage mask
4	UVSUP5_EN	R/W	1b	VSUP5 undervoltage mask
3	UVSUP3_EN	R/W	1b	UVSUP3 undervoltage mask
2	UVCC1_EN	R/W	1b	VCC1 undervoltage mask
1	TSD_SBC_EN	R/W	1b	Masking bit for interrupt due to SBC Thermal Shutdown
0	SME_EN	R	1b	SME interrupt enable (always enabled)

9.1.71 INT_EN_3 Register (Address = 58h) [Reset = FEh]

INT_EN_3 is shown in Table 9-73.

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Table 9-73 INT_EN_3 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	SPIERR_EN	R/W	1b	SPI error interrupt mask
6	SWERR_EN	R/W	1b	Selective wake error mask
5	FSM_EN	R/W	1b	Fail-safe status flag mask
4	CRCERR_EN	R/W	1b	SPI CRC error interrupt mask
3	VCC1SC_EN	R/W	1b	VCC1 short circuit interrupt mask
2	RSRT_CNT_EN	R/W	1b	Restart counter exceeded programmed count mask
1	TSD_CAN_EN	R	1b	Masking bit for CAN/VCC2 thermal shutdown
0	RESERVED	R	0b	Reserved

9.1.72 INT_EN_CANBUS_1 Register (Address = 59h) [Reset = BFh]

INT_EN_CANBUS_1 is shown in Table 9-74.

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Table 9-74 INT_EN_CANBUS_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	UVCAN_EN	R/W	1b	UVCAN interrupt mask
6	RESERVED	R	0b	Reserved
5	CANHCANL_EN	R/W	1b	Masking bit for CANH and CANL shorted together fault interrupt
4	CANHBAT_EN	R/W	1b	Masking bit for CANH shorted to Vbat fault interrupt
3	CANLGND_EN	R/W	1b	CANL shorted to GND enable
2	CANBUSOPEN_EN	R/W	1b	CAN bus open enable
1	CANBUSGND_EN	R/W	1b	CAN bus shorted to GND enable
0	CANBUSBAT_EN	R/W	1b	CAN bus shorted to Vbat enable

9.1.73 INT_4 Register (Address = 5Ah) [Reset = 00h]

INT_4 is shown in Table 9-75.

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Table 9-75 INT_4 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0b	Reserved
6	RESERVED	R	0b	Reserved
5	RESERVED	R	0b	Reserved
4	CYC_WUP	R/W1C	0b	Cyclic wake interrupt via internal timer
3	MODE_ERR	R/W1C	0b	Illegal transceiver state for mode change request
2	OVHSS	R/W1C	0b	VHSS over-voltage for high-side switches
1	EEPROM_CRC_INT	R/W1C	0b	EEPROM CRC check fail
0	UVHSS	R/W1C	0b	VHSS under-voltage for high-side switches

9.1.74 INT_6 Register (Address = 5Ch) [Reset = 00h]

INT_6 is shown in Table 9-76.

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Table 9-76 INT_6 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	TSDW	R/W1C	0b	Thermal shutdown warning
6	UVCC1PW	R/W1C	0b	VCC1 undervoltage pre-warning
5	RESERVED	R	0b	Reserved
4	RESERVED	R	0b	Reserved
3	RESERVED	R	0b	Reserved
2	UVCC2	R/W1C	0b	VCC2 pin undervoltage
1	OVCC2	R/W1C	0b	VCC2 pin overvoltage
0	VCC2SC	R/W1C	0b	VCC2 pin short circuit

9.1.75 INT_EN_4 Register (Address = 5Eh) [Reset = 1Fh]

INT_EN_4 is shown in Table 9-77.

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Table 9-77 INT_EN_4 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0b	Reserved
6	RESERVED	R	0b	Reserved
5	RESERVED	R	0b	Reserved
4	CYC_WUP_EN	R/W	1b	Masking bit for cyclic wake interrupt
3	MODE_ERR_EN	R/W	1b	Illegal transceiver state for mode change request mask
2	OVHSS_EN	R/W	1b	VHSS over-voltage for high-side switches mask
1	EEPROM_CRC_INT_EN	R/W	1b	EEPROM CRC check fail mask
0	UVHSS_EN	R/W	1b	VHSS under-voltage for high-side switches mask

9.1.76 INT_EN_6 Register (Address = 60h) [Reset = C7h]

INT_EN_6 is shown in Table 9-78.

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Table 9-78 INT_EN_6 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	TSDW_EN	R/W1C	1b	Thermal shutdown warning mask
6	UVCC1PW_EN	R/W1C	1b	VCC1 undervoltage pre-warning mask
5	RESERVED	R	0b	Reserved
4	RESERVED	R	0b	Reserved
3	RESERVED	R	0b	Reserved
2	UVCC2_EN	R/W	1b	VCC2 pin undervoltage mask
1	OVCC2_EN	R/W	1b	VCC2 pin overvoltage mask
0	VCC2SC_EN	R/W	1b	VCC2 pin short circuit mask

9.1.77 INT_EN_7 Register (Address = 62h) [Reset = FFh]

INT_EN_7 is shown in Table 9-79.

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Table 9-79 INT_EN_7 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	HSSOC1_EN	R/W	1b	High side switch 1 over current interrupt mask
6	HSSOL1_EN	R/W	1b	High side switch 1 open load interrupt mask
5	HSSOC2_EN	R/W	1b	High side switch 2 over current interrupt mask
4	HSSOL2_EN	R/W	1b	High side switch 2 open load interrupt mask
3	HSSOC3_EN	R/W	1b	High side switch 3 over current interrupt mask
2	HSSOL3_EN	R/W	1b	High side switch 3 open load interrupt mask
1	HSSOC4_EN	R/W	1b	High side switch 4 over current interrupt mask
0	HSSOL4_EN	R/W	1b	High side switch 4 open load interrupt mask

9.1.78 BUCK_CONFIG1 Register (Address = 65h) [Reset = 28h]

BUCK_CONFIG1 is shown in Table 9-80.

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Table 9-80 BUCK_CONFIG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RSVD (REV_ID = 20h)	R/W	00b	REV_ID: 20h RESERVED
7-6	SS_MOD_FREQ (REV_ID = 21h)	R/W	00b	REV_ID: 21h Spread Spectrum Modulation frequency spread options. NOTE: These bits are available only with REV_ID = 21h (silicon revision 2.1). NOTE: Switching frequency of 1.8 MHz with Spread Spectrum enabled can create emissions in the AM band. Recommended to use 4% delta fc modulation option to minimize interference in the AM band 00b = Off 01b = 4% delta fc 10b = 8% delta fc 11b = Reserved
5-4	BUCK_FSW	R/W	10b	Buck regulator switching frequency setting 00b = 1.8 MHz 01b = 2.0 MHz 10b = 2.2 MHz 11b = 2.4 MHz
3	PWM_PFM_CNTL_NORMAL	R/W	1b	PFM and PWM Mode Configuration in Normal mode 0b = Auto (Automatic transition between PFM and PWM mode) 1b = PWM
2	PWM_PFM_CNTL_STDBY_SLP	R/W	0b	PFM and PWM Mode Configuration in Standby/Sleep mode 0b = Auto (Automatic transition between PFM and PWM mode) 1b = PWM
1	RSVD (REV_ID = 20h)	R/W	0b	REV_ID: 20h Reserved bit when REV_ID is 20h (Silicon revision 2.0). Note: Do not set this bit in ES_2.0
1	PRSS_EN (REV_ID = 21h)	R/W	0b	REV_ID: 21h Enables the Pseudo Random Spread Spectrum (PRSS) NOTE: This bit is available only with REV_ID = 21h (Silicon rev 2.1) 0b = Linear Spread Spectrum 1b = Pseudo Random Spread Spectrum
0	ICC1_CUR_LIMIT	R/W	0b	Current limit threshold for the buck regulator 0b = High threshold (1A load) 1b = Low threshold (500mA load)

9.1.79 ID_PIN_STATUS Register (Address = 78h) [Reset = 00h]

ID_PIN_STATUS is shown in Table 9-81.

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Table 9-81 ID_PIN_STATUS Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	ID4_STAT	R/W0C	00b	Status of the ID4 pin connection Note: If WAKE_ID4_PU_PD register bit is set to 01b (pulldown) or 10b (pull-up), the status bits will be reset to 00b. WAKE4_STAT bit will reflect the real time pin logic of ID4 pin in such a case. 00b = Unknown 01b = Connected to GND 10b = Connected to VSUP 11b = Floating
5-4	ID3_STAT	R/W0C	00b	Status of the ID3 pin connection Note: If WAKE_ID3_PU_PD register bit is set to 01b (pulldown) or 10b (pull-up), the status bits will be reset to 00b. WAKE3_STAT bit will reflect the real time pin logic of ID3 pin in such a case. 00b = Unknown 01b = Connected to GND 10b = Connected to VSUP 11b = Floating
3-2	ID2_STAT	R/W0C	00b	Status of the ID2 pin connection Note: If WAKE_ID2_PU_PD register bit is set to 01b (pulldown) or 10b (pull-up), the status bits will be reset to 00b. WAKE2_STAT bit will reflect the real time pin logic of ID2 pin in such a case. 00b = Unknown 01b = Connected to GND 10b = Connected to VSUP 11b = Floating
1-0	ID1_STAT	R/W0C	00b	Status of the ID1 pin connection Note: If WAKE_ID1_PU_PD register bit is set to 01b (pulldown) or 10b (pull-up), the status bits will be reset to 00b. WAKE1_STAT bit will reflect the real time pin logic of ID1 pin in such a case. 00b = Unknown 01b = Connected to GND 10b = Connected to VSUP 11b = Floating

9.1.80 WAKE_ID_CONFIG1 Register (Address = 79h) [Reset = 66h]

WAKE_ID_CONFIG1 is shown in Table 9-82.

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Table 9-82 WAKE_ID_CONFIG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	ID2_EN	R/W	0b	Enables/disables ID2 functionality Note: If both ID2_EN and WAKE2_PIN_SET are set to 1b, the device will ignore WAKE2_PIN_SET setting and the ID function will be enabled at the WAKE2/ID2 pin 0b = ID2 pin disabled 1b = ID2 pin enabled
6-5	WAKE_ID2_PU_PD	R/W	11b	ID2 configuration for pull-up, pull-down, automatic or disabled Note: Only the Automatic selection (11b) will update the ID2_STAT register bit 00b = Neither pull-up nor pull-down activated 01b = Pull-down activated 10b = Pull-up activated 11b = Automatic selection of pull-up/pull-down
4	ID2_PD_VALUE	R	0b	ID2 pin pull-down current strength setting 0b = 3 mA 1b = 10 mA
3	ID1_EN	R/W	0b	Enables/disables ID1 functionality Note: If both ID1_EN and WAKE1_PIN_SET are set to 1b, the device will ignore WAKE1_PIN_SET setting and the ID function will be enabled at the WAKE1/ID1 pin 0b = ID1 pin disabled 1b = ID1 pin enabled
2-1	WAKE_ID1_PU_PD	R/W	11b	ID1 configuration for pull-up, pull-down, automatic or disabled Note: Only the Automatic selection (11b) will update the ID1_STAT register bit 00b = Neither pull-up nor pull-down activated 01b = Pull-down activated 10b = Pull-up activated 11b = Automatic selection of pull-up/pull-down
0	ID1_PD_VALUE	R	0b	ID1 pin pull-down current strength setting 0b = 3 mA 1b = 10 mA

9.1.81 WAKE_ID_CONFIG2 Register (Address = 7Ah) [Reset = 66h]

WAKE_ID_CONFIG2 is shown in Table 9-83.

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Table 9-83 WAKE_ID_CONFIG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	ID4_EN	R/W	0b	Enables/disables ID4 functionality Note: If both ID4_EN and WAKE4_PIN_SET are set to 1b, the device will ignore WAKE4_PIN_SET setting and the ID function will be enabled at the WAKE4/ID4 pin 0b = ID4 pin disabled 1b = ID4 pin enabled
6-5	WAKE_ID4_PU_PD	R/W	11b	ID4 configuration for pull-up, pull-down, automatic or disabled Note: Only the Automatic selection (11b) will update the ID4_STAT register bit 00b = Neither pull-up nor pull-down activated 01b = Pull-down activated 10b = Pull-up activated 11b = Automatic selection of pull-up/pull-down
4	ID4_PD_VALUE	R	0b	ID4 pin pull-down current strength setting 0b = 3 mA 1b = 10 mA
3	ID3_EN	R/W	0b	Enables/disables ID3 functionality Note: If both ID3_EN and WAKE3_PIN_SET are set to 1b, the device will ignore WAKE3_PIN_SET setting and the ID function will be enabled at the WAKE3/ID3 pin 0b = ID3 pin disabled 1b = ID3 pin enabled
2-1	WAKE_ID3_PU_PD	R/W	11b	ID3 configuration for pull-up, pull-down, automatic or disabled Note: Only the Automatic selection (11b) will update the ID3_STAT register bit 00b = Neither pull-up nor pull-down activated 01b = Pull-down activated 10b = Pull-up activated 11b = Automatic selection of pull-up/pull-down
0	ID3_PD_VALUE	R	0b	ID3 pin pull-down current strength setting 0b = 3 mA 1b = 10 mA

9.1.82 WAKE_PIN_CONFIG5 Register (Address = 7Bh) [Reset = 20h]

WAKE_PIN_CONFIG5 is shown in Table 9-84.

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Table 9-84 WAKE_PIN_CONFIG5 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	WAKE4_SENSE	R/W	0b	WAKE4 pin configured for static or cyclic sensing wake 0b = Static sensing 1b = Cyclic sensing
6	WAKE4_STAT	RH	0b	Provides status of WAKE4 pin. 0b = Low 1b = High
5-4	WAKE4_LEVEL	R/W	10b	Sets the WAKE4 pin input thresholds 00b = VCC1 based 01b = 2.5 V 10b = 4V 11b = 6 V
3-0	RESERVED	R	0b	Reserved