SLLSFP2 September   2024 TUSB1021-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 USB 3.2
      2. 7.3.2 4-Level Inputs
      3. 7.3.3 Receiver Linear Equalization
    4. 7.4 Device Functional Modes
      1. 7.4.1 USB 3.2 2:1 MUX Description
      2. 7.4.2 Linear EQ Configuration
      3. 7.4.3 USB3.2 Modes
      4. 7.4.4 Operation Timing – Power Up
    5. 7.5 Programming
      1. 7.5.1 TUSB1021-Q1 I2C Target Behavior
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 ESD Protection
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Register Maps
    1. 9.1 General Register (address = 0x0A) [reset = 00000001]
    2. 9.2 USB3.2 Control/Status Registers (address = 0x20) [reset = 00000000]
    3. 9.3 USB3.2 Control/Status Registers (address = 0x21) [reset = 00000000]
    4. 9.4 USB3.2 Control/Status Registers (address = 0x22) [reset = 00000000]
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

9.4 USB3.2 Control/Status Registers (address = 0x22) [reset = 00000000]

Figure 9-4 USB3.2 Control/Status Registers (0x22)
7 6 5 4 3 2 1 0
CM_ACTIVE LFPS_EQ U2U3_LFPS_DEBOUNCE DISABLE_U2U3_RXDET DFP_RXDET_INTERVAL USB3_COMPLIANCE_CTRL
R/U R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-5 USB3.2 Control/Status Registers (0x22)
Bit Field Type Reset Description
7 CM_ACTIVE R/U 0 0: Device not in USB 3.2 compliance mode. (Default)
1: Device in USB 3.2 compliance mode
6 LFPS_EQ R/W 0 Controls whether settings of EQ based on EQ1_SEL, EQ2_SEL and SSEQ_SEL applies to received LFPS signal.
0: EQ set to zero when receiving LFPS (default)
1: EQ set to EQ1_SEL, EQ2_SEL, and SSEQ_SEL when receiving LFPS.
5 U2U3_LFPS_DEBOUNCE R/W 0 0: No debounce of LFPS before U2/U3 exit. (Default)
1: 200µs debounce of LFPS before U2/U3 exit.
4 DISABLE_U2U3_RXDET R/W 0 0: Rx.Detect in U2/U3 enabled. (Default)
1: Rx.Detect in U2/U3 disabled.
3:2 DFP_RXDET_INTERVAL R/W 00 This field controls the Rx.Detect interval for the Downstream facing port (TX1P/N and TX2P/N).
00: 8ms
01: 12ms (default)
10: Reserved
11: Reserved
1:0 USB3_COMPLIANCE_CTRL R/W 00 00: FSM determined compliance mode. (Default)
01: Compliance Mode enabled in DFP direction (SSTX -> TX1/TX2)
10: Compliance Mode enabled in UFP direction (RX1/RX2 -> SSRX)
11: Compliance Mode Disabled.