SLLSFP2 September   2024 TUSB1021-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 USB 3.2
      2. 7.3.2 4-Level Inputs
      3. 7.3.3 Receiver Linear Equalization
    4. 7.4 Device Functional Modes
      1. 7.4.1 USB 3.2 2:1 MUX Description
      2. 7.4.2 Linear EQ Configuration
      3. 7.4.3 USB3.2 Modes
      4. 7.4.4 Operation Timing – Power Up
    5. 7.5 Programming
      1. 7.5.1 TUSB1021-Q1 I2C Target Behavior
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 ESD Protection
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Register Maps
    1. 9.1 General Register (address = 0x0A) [reset = 00000001]
    2. 9.2 USB3.2 Control/Status Registers (address = 0x20) [reset = 00000000]
    3. 9.3 USB3.2 Control/Status Registers (address = 0x21) [reset = 00000000]
    4. 9.4 USB3.2 Control/Status Registers (address = 0x22) [reset = 00000000]
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

9.2 USB3.2 Control/Status Registers (address = 0x20) [reset = 00000000]

Figure 9-2 USB3.2 Control/Status Registers (0x20)
76543210
EQ2_SELEQ1_SEL
R/W/UR/W/U
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-3 USB3.2 Control/Status Registers (0x20)
BitFieldTypeResetDescription
7:4EQ2_SELR/W/U0000Field selects EQ level for USB3.2 RX2 receiver. When EQ_OVERRIDE = 1’b0, this field reflects the sampled state of EQ[1:0] pins. When EQ_OVERRIDE = 1’b1, software can change the EQ setting for USB3.2 RX2 receiver based on value written to this field.
3:0EQ1_SELR/W/U0000Field selects EQ level for USB3.2 RX1 receiver. When EQ_OVERRIDE = 1’b0, this field reflects the sampled state of EQ[1:0] pins. When EQ_OVERRIDE = 1’b1, software can change the EQ setting for USB3.2 RX1 receiver based on value written to this field.