SLLSG10A November   2024  – February 2025 TDP142-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Power Supply Characteristics
    6. 5.6 Control I/O DC Electrical Characteristics
    7. 5.7 DP Electrical Characteristics
    8. 5.8 Switching Characteristics
    9. 5.9 Typical Characteristics
  7.   Parameter Measurement Information
  8. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 DisplayPort
      2. 6.3.2 Configuration Jumper Levels
      3. 6.3.3 Receiver Linear Equalization
    4. 6.4 Device Functional Modes
      1. 6.4.1 Device Configuration in GPIO Mode
      2. 6.4.2 Device Configuration in I2C Mode
      3. 6.4.3 Linear EQ Configuration
      4. 6.4.4 Operation Timing – Power Up
    5. 6.5 Programming
  9. 7 Register Maps
    1. 7.1 TDP142-Q1 Registers
  10. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 ESD Protection
    2. 8.2 Typical Application
      1. 8.2.1 Source Application Implementation
        1. 8.2.1.1 Design Requirement
        2. 8.2.1.2 Detail Design Procedure
      2. 8.2.2 Sink Application Implementation
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  11. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  12. 10Revision History
  13. 11Mechanical, Packaging, and Orderable Information

7.1 TDP142-Q1 Registers

Table 7-1 lists the TDP142-Q1 registers. All register offset addresses not listed in Table 7-1 should be considered as reserved locations and the register contents should not be modified.

Table 7-1 TDP142-Q1 Registers
Offset Acronym Register Name Section
0xA General_1 General Register Go
0x10 DP01EQ_SEL DisplayPort Lane 0 and 1 EQ Control Go
0x11 DP23EQ_SEL DisplayPort Lane 2 and 3 EQ Control Go
0x12 DisplayPort_1 AUX Snoop Status Go
0x13 DisplayPort_2 DP Lane Enable/Disable Control Go
0x32 VOD_CTRL VOD Linearity Go

Complex bit access types are encoded to fit into small table cells. Table 7-2 shows the codes that are used for access types in this section.

Table 7-2 TDP142-Q1 Access Type Codes
Access Type Code Description
Read Type
R R Read
RH R
H		 Read
Set or cleared by hardware
Write Type
W W Write
W1S W
1S		 Write
1 to set
WS W Write
Reset or Default Value
-n Value after reset or the default value

7.1.1 General_1 Register (Offset = 0xA) [reset = 0x1]

General_1 is shown in Table 7-3.

Return to the Summary Table.

This register is used to select between disabled and DisplayPort modes. Software can set the EQ_OVERRIDE bit to use the EQ registers instead of pins.

Table 7-3 General_1 Register Field Descriptions
Bit Field Type Reset Description
7 RESERVED R/W 0x0

Reserved
6 RESERVED R 0x0

Reserved
5 SWAP_HPDIN R/W 0x0

Controls which pin HPDIN is derived from.

0x0 = HPDIN is in default location

0x1 = HPDIN location is swapped (PIN 23 to PIN 32, or PIN 32 to PIN 23).
4 EQ_OVERRIDE R/W 0x0

Setting this field allows software to use EQ settings from registers instead of value sampled from pins.

0x0 = EQ settings based on sampled state of EQ pins.

0x1 = EQ settings based on programmed value of each of the EQ registers.
3 HPDIN_OVERRIDE R/W 0x0

Overrides HPDIN pin state.

0x0 = HPD_IN based on HPD_IN pin.

0x1 = HPD_IN high.
2 RESERVED R/W 0x0 RESERVED
1-0 CTLSEL R/W 0x1

Upon power-on, software must write 0x2 to enable DisplayPort functionality. If DisplayPort functionality is not required, then software must write 0x0 to disable DisplayPort

0x0 = Disabled. DP disabled and lowest power state

0x1 = DP disabled but not lowest power state.

0x2 = DisplayPort enabled.

0x3 = Reserved

7.1.2 DP01EQ_SEL Register (Offset = 0x10) [reset = 0x0]

DP01EQ_SEL is shown in Table 7-4.

Return to the Summary Table.

This register controls the receiver equalization setting for the DisplayPort receivers 0 and 1.

Table 7-4 DP01EQ_SEL Register Field Descriptions
Bit Field Type Reset Description
7-4 DP1EQ_SEL RH/W 0x0

Field selects EQ for DP lane 1 pins. When EQ_OVERRIDE = 0b, this field reflects the sampled state of DPEQ[1:0] pins. When EQ_OVERRIDE = 1b, software can change the EQ setting for DP Lane 1 based on value written to this field.
3-0 DP0EQ_SEL RH/W 0x0

Field selects EQ for DP lane 0 pins. When EQ_OVERRIDE = 0b, this field reflects the sampled state of DPEQ[1:0] pins. When EQ_OVERRIDE = 1b, software can change the EQ setting for DP Lane 0 based on value written to this field.

7.1.3 DP23EQ_SEL Register (Offset = 0x11) [reset = 0x0]

DP23EQ_SEL is shown in Table 7-5.

Return to the Summary Table.

This register controls the receiver equalization setting for the DisplayPort receivers 2 and 3.

Table 7-5 DP23EQ_SEL Register Field Descriptions
Bit Field Type Reset Description
7-4 DP3EQ_SEL RH/W 0x0

Field selects EQ for DP lane 3 pins. When EQ_OVERRIDE = 0b, this field reflects the sampled state of DPEQ[1:0] pins. When EQ_OVERRIDE = 1b, software can change the EQ setting for DP Lane 3 based on value written to this field.
3-0 DP2EQ_SEL RH/W 0x0

Field selects EQ for DP lane 2 pins. When EQ_OVERRIDE = 0b, this field reflects the sampled state of DPEQ[1:0] pins. When EQ_OVERRIDE = 1b, software can change the EQ setting for DP Lane 2 based on value written to this field.

7.1.4 DisplayPort_1 Register (Offset = 0x12) [reset = 0x0]

DisplayPort_1 is shown in Table 7-6.

Return to the Summary Table.

This register provides status of AUX snooping when AUX Snooping is enabled.

Table 7-6 DisplayPort_1 Register Field Descriptions
Bit Field Type Reset Description
7 RESERVED R 0x0

Reserved
6-5 SET_POWER_STATE RH 0x0

This field represents the snooped value of the AUX write to DPCD address 0x00600. When AUX_SNOOP_DISABLE = 0b, the enable/disable of DP lanes based on the snooped value. When AUX_SNOOP_DISABLE = 1b, then DP lane enable/disable are determined by state of DPx_DISABLE registers, where x = 0, 1, 2, or 3. This field is reset to 0h by hardware when CTLSEL1 changes from a 1b to a 0b.
4-0 LANE_COUNT_SET RH 0x0

This field represents the snooped value of AUX write to DPCD address 0x00101 register. When AUX_SNOOP_DISABLE = 0b, DP lanes enabled specified by the snoop value. Unused DP lanes is disabled to save power. When AUX_SNOOP_DISABLE = 1b, then DP lanes enable/disable are determined by DPx_DISABLE registers, where x = 0, 1, 2, or 3. This field is reset to 0h by hardware when CTLSEL1 changes from a 1b to a 0b.

7.1.5 DisplayPort_2 Register (Offset = 0x13) [reset = 0x0]

DisplayPort_2 is shown in Table 7-7.

Return to the Summary Table.

This register provides controls for enabling and disabling AUX snooping and individual DP lanes.

Table 7-7 DisplayPort_2 Register Field Descriptions
Bit Field Type Reset Description
7 AUX_SNOOP_DISABLE R/W 0x0

Controls whether DP lanes are enabled based on AUX snooped value or registers.

0x0 = AUX snoop enabled.

0x1 = AUX snoop disabled. DP lanes are controlled by registers.
6 RESERVED R 0x0

Reserved
5-4 RESERVED R/W 0x0

Reserved
3 DP3_DISABLE R/W 0x0

When AUX_SNOOP_DISABLE = 1b, this field can be used to enable or disable DP lane 3. When AUX_SNOOP_DISABLE = 0b, changes to this field have no effect on lane 3 functionality.

0x0 = DP Lane 3 enabled.

0x1 = DP Lane 3 disabled.
2 DP2_DISABLE R/W 0x0

When AUX_SNOOP_DISABLE = 1b, this field can be used to enable or disable DP lane 2. When AUX_SNOOP_DISABLE = 0b, changes to this field have no effect on lane 2 functionality.

0x0 = DP Lane 2 enabled.

0x1 = DP Lane 2 disabled.
1 DP1_DISABLE R/W 0x0

When AUX_SNOOP_DISABLE = 1b, this field can be used to enable or disable DP lane 1. When AUX_SNOOP_DISABLE = 0b, changes to this field have no effect on lane 1 functionality.

0x0 = DP Lane 1 enabled.

0x1 = DP Lane 1 disabled.
0 DP0_DISABLE R/W 0x0

When AUX_SNOOP_DISABLE = 1b, this field can be used to enable or disable DP lane 0. When AUX_SNOOP_DISABLE = 0b, changes to this field have no effect on lane 0 functionality.

0x0 = DP Lane 0 enabled.

0x1 = DP Lane 0 disabled.

7.1.6 VOD_CTRL Register (Offset = 0x32) [reset = 0x40]

VOD_CTRL is shown in Table 7-8.

Return to the Summary Table.

This register controls the transmitters output linearity range.

Table 7-8 VOD_CTRL Register Field Descriptions
Bit Field Type Reset Description
7-6

Reserved

 R/W 0x1

Reserved
5-4 DP_VOD R/W 0x0

VOD linearity control for DP paths.

0x0 = LINR_L3 (highest)

0x1 = LINR_L2

0x2 = LINR_L1

0x3 = LINR_L0 (lowest)
3-0

Reserved

 R/W 0x0

Reserved