SLLSG22A December   2024  – February 2025 ISO6520-Q1 , ISO6521-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Package Characteristics
    6. 5.6  Electrical Characteristics—5-V Supply
    7. 5.7  Supply Current Characteristics—5-V Supply
    8. 5.8  Electrical Characteristics—3.3-V Supply
    9. 5.9  Supply Current Characteristics—3.3-V Supply
    10. 5.10 Electrical Characteristics—2.5-V Supply 
    11. 5.11 Supply Current Characteristics—2.5-V Supply
    12. 5.12 Electrical Characteristics—1.8-V Supply
    13. 5.13 Supply Current Characteristics—1.8-V Supply
    14. 5.14 Switching Characteristics—5-V Supply
    15. 5.15 Switching Characteristics—3.3-V Supply
    16. 5.16 Switching Characteristics—2.5-V Supply
    17. 5.17 Switching Characteristics—1.8-V Supply
    18. 5.18 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device I/O Schematics
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 PCB Material
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5.15 Switching Characteristics—3.3-V Supply

VCC1 = VCC2 = 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
tPLH, tPHLPropagation delay timeSee Figure 6-11118ns
tP(dft)Propagation delay drift9.2ps/℃
tUIMinimum pulse widthSee Figure 6-120ns
PWDPulse width distortion(1) |tPHL – tPLH|See Figure 6-10.57ns
tsk(o)Channel-to-channel output skew time (2)Same direction channels6ns
tsk(p-p)Part-to-part skew time (3)6ns
trOutput signal rise timeSee Figure 6-11.63.2ns
tfOutput signal fall time1.63.2ns
tPUTime from UVLO to valid output data300μs
tDODefault output delay time from input power lossMeasured from the time VCC goes
below 1.2V. See Figure 6-2		0.10.3μs
tieTime interval error216 – 1 PRBS data at 50 Mbps1ns
(1) Also known as pulse skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads.