SLOS893D September   2014  – August 2025 DRV2624

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Test Setup for Graphs
      1. 6.1.1 Default Test Conditions
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Support for ERM and LRA Actuators
      2. 7.3.2  Smart-Loop Architecture
        1. 7.3.2.1 Auto-Resonance Engine for LRA
        2. 7.3.2.2 Real-Time Resonance-Frequency Reporting for LRA
        3. 7.3.2.3 Automatic Switch to Open-Loop for LRA
        4. 7.3.2.4 Automatic Overdrive and Braking
          1. 7.3.2.4.1 Startup Boost
          2. 7.3.2.4.2 Brake Factor
        5. 7.3.2.5 Automatic Level Calibration
          1. 7.3.2.5.1 Automatic Compensation for Resistive Losses
          2. 7.3.2.5.2 Automatic Back-EMF Normalization
          3. 7.3.2.5.3 Calibration Time Adjustment
          4. 7.3.2.5.4 Loop-Gain Control
          5. 7.3.2.5.5 Back-EMF Gain Control
        6. 7.3.2.6 Actuator Diagnostics
        7. 7.3.2.7 Automatic Re-Synchronization
      3. 7.3.3  Open-Loop Operation
        1. 7.3.3.1 Waveform Shape Selection for LRA
        2. 7.3.3.2 Automatic Braking in Open Loop
      4. 7.3.4  Flexible Front-End Interface
        1. 7.3.4.1 Internal Memory Interface
          1. 7.3.4.1.1 Library Parameterization
          2. 7.3.4.1.2 Playback Interval
          3. 7.3.4.1.3 Waveform Sequencer
        2. 7.3.4.2 Real-Time Playback (RTP) Interface
        3. 7.3.4.3 Process Trigger
      5. 7.3.5  Noise Gate Control
      6. 7.3.6  Edge Rate Control
      7. 7.3.7  Constant Vibration Strength
      8. 7.3.8  Battery Voltage Reporting
      9. 7.3.9  Ultra Low-Power Shutdown
      10. 7.3.10 Automatic Go-To-Stand-by (Low Power)
      11. 7.3.11 I2C Watchdog Timer
      12. 7.3.12 Device Protection
        1. 7.3.12.1 Thermal Sensor
        2. 7.3.12.2 Over-Current Protection
        3. 7.3.12.3 VDD UVLO Protection
        4. 7.3.12.4 Brownout Protection
      13. 7.3.13 POR
      14. 7.3.14 Silicon Revision Control
      15. 7.3.15 Support for LRA and ERM Actuators
      16. 7.3.16 Multi-Purpose Pin Functionality
        1. 7.3.16.1 Trigger-Pulse Functionality
        2. 7.3.16.2 Trigger-Level (Enable) Functionality
        3. 7.3.16.3 Interrupt Functionality
      17. 7.3.17 Automatic Transition to Standby State
      18. 7.3.18 Automatic Brake into Standby
      19. 7.3.19 Battery Monitoring and Power Preservation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power States
      2. 7.4.2 Operation With VDD < 2.5 V (Minimum VDD)
      3. 7.4.3 Operation With VDD > 6 V (Absolute Maximum VDD)
      4. 7.4.4 Operation in Shutdown State
      5. 7.4.5 Operation in STANDBY State
      6. 7.4.6 Operation in ACTIVE State
      7. 7.4.7 Changing Modes of Operation
    5. 7.5 Operation During Exceptional Conditions
      1. 7.5.1 Operation With No Actuator Attached
      2. 7.5.2 Operation With a Non-Moving Actuator Attached
      3. 7.5.3 Operation With a Short at REG Pin
      4. 7.5.4 Operation With a Short at OUT+, OUT–, or Both
    6. 7.6 Programming
      1. 7.6.1  Auto-Resonance Engine Programming for the LRA
        1. 7.6.1.1 Drive-Time Programming
        2. 7.6.1.2 Current-Dissipation Time Programming
        3. 7.6.1.3 Blanking Time Programming
        4. 7.6.1.4 Zero-Crossing Detect-Time Programming
      2. 7.6.2  Automatic-Level Calibration Programming
        1. 7.6.2.1 Rated Voltage Programming
        2. 7.6.2.2 Overdrive Voltage-Clamp Programming
      3. 7.6.3  I2C Interface
        1. 7.6.3.1 TI Haptic Broadcast Mode
        2. 7.6.3.2 I2C Communication Availability
        3. 7.6.3.3 General I2C Operation
        4. 7.6.3.4 Single-Byte and Multiple-Byte Transfers
        5. 7.6.3.5 Single-Byte Write
        6. 7.6.3.6 Multiple-Byte Write and Incremental Multiple-Byte Write
        7. 7.6.3.7 Single-Byte Read
        8. 7.6.3.8 Multiple-Byte Read
      4. 7.6.4  Programming for Open-Loop Operation
        1. 7.6.4.1 Programming for ERM Open-Loop Operation
        2. 7.6.4.2 Programming for LRA Open-Loop Operation
      5. 7.6.5  Programming for Closed-Loop Operation
      6. 7.6.6  Diagnostics Routine
      7. 7.6.7  Calibration Routine
      8. 7.6.8  Waveform Playback Programming
        1. 7.6.8.1 Data Formats for Waveform Playback
        2. 7.6.8.2 Open-Loop Mode
        3. 7.6.8.3 Closed-Loop Mode
      9. 7.6.9  Waveform Setup and Playback
        1. 7.6.9.1 Waveform Playback Using RTP Mode
        2. 7.6.9.2 Loading Data to RAM
          1. 7.6.9.2.1 Header Format
          2. 7.6.9.2.2 RAM Waveform Data Format
        3. 7.6.9.3 Waveform Sequencer
        4. 7.6.9.4 Waveform Playback Triggers
          1. 7.6.9.4.1 Playback Trigger Without Automatic Brake into Standby
            1. 7.6.9.4.1.1 Playback Trigger With Automatic Brake into Standby (SimpleDrive)
      10. 7.6.10 120
  9. 8 Register Map
    1. 8.1  Address: 0x00
    2. 8.2  Address: 0x01
    3. 8.3  Address: 0x02
    4. 8.4  Address: 0x03
    5. 8.5  Address: 0x04
    6. 8.6  Address: 0x05
    7. 8.7  Address: 0x06
    8. 8.8  Address: 0x07
    9. 8.9  Address: 0x08
    10. 8.10 Address: 0x09
    11. 8.11 Address: 0x0A
    12. 8.12 Address: 0x0B
    13. 8.13 Address: 0x0C
    14. 8.14 Address: 0x0D
    15. 8.15 Address: 0x0E
    16. 8.16 Address: 0x0F
    17. 8.17 Address: 0x10
    18. 8.18 Address: 0x11
    19. 8.19 Address: 0x12
    20. 8.20 Address: 0x13
    21. 8.21 Address: 0x14
    22. 8.22 Address: 0x15
    23. 8.23 Address: 0x16
    24. 8.24 Address: 0x17
    25. 8.25 Address: 0x18
    26. 8.26 Address: 0x19
    27. 8.27 Address: 0x1A
    28. 8.28 Address: 0x1B
    29. 8.29 Address: 0x1C
    30. 8.30 Address: 0x1D
    31. 8.31 Address: 0x1F
    32. 8.32 Address: 0x20
    33. 8.33 Address: 0x21
    34. 8.34 Address: 0x22
    35. 8.35 Address: 0x23
    36. 8.36 Address: 0x24
    37. 8.37 Address: 0x25
    38. 8.38 Address: 0x26
    39. 8.39 Address: 0x27
    40. 8.40 Address: 0x28
    41. 8.41 Address: 0x29
    42. 8.42 Address: 0x2A
    43. 8.43 Address: 0x2C
    44. 8.44 Address: 0x2E
    45. 8.45 Address: 0x2F
    46. 8.46 Address: 0x30
    47. 8.47 Address: 0xFD
    48. 8.48 Address: 0xFE
    49. 8.49 Address: 0xFF
  10.   Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Actuator Selection
          1. 9.2.2.1.1 Eccentric Rotating-Mass Motors (ERM)
          2. 9.2.2.1.2 Linear Resonance Actuators (LRA)
            1. 9.2.2.1.2.1 Auto-Resonance Engine for LRA
        2. 9.2.2.2 Capacitor Selection
        3. 9.2.2.3 Interface Selection
        4. 9.2.2.4 Power Supply Selection
      3. 9.2.3 Application Curves
    3. 9.3 Initialization Set Up
      1. 9.3.1 Initialization Procedure
      2. 9.3.2 Typical Usage Examples
        1. 9.3.2.1 Play a Waveform or Waveform Sequence from the RAM Waveform Memory
        2. 9.3.2.2 Play a Real-Time Playback (RTP) Waveform
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Examples
  11. 9 Device and Documentation Support
    1. 9.1 Device Support
    2. 9.2 Trademarks
  12. 10Revision History
  13. 11Mechanical, Packaging, and Orderable Information

7.3.19 Battery Monitoring and Power Preservation

The DRV2624 device continuously monitors the VDD voltage. In the event of a VDD voltage glitch that goes below the UVLO_THRES[2:0] voltage, the DRV2624 immediately stops any playback and goes into standby state. The UVLO status bit asserts and, if configured, the TRIG/INTZ pin is asserted. Note that going into standby due to a VDD glitch bypasses any braking, even if AUTO_BRK_INTO_STBY is enabled. I2C communication is not interrupted if a UVLO condition happens. However, because a UVLO condition can potentially corrupt such communication, TI recommends checking the UVLO flag after I2C transactions as a way to verify that the content was not corrupted in the process.

The DRV2624 also features a battery preservation mode that monitors the battery, and if VDD voltage drops below a specified threshold (see BAT_LIFE_EXT_LVL1[7:0] and BAT_LIFE_EXT_LVL2[7:0] parameters) automatically clamps the maximum output voltage, as specified by the user (see OD_CLAMP_LVL1[7:0] and OD_CLAMP_LVL2[7:0] parameters).