SLPS755B October   2023  – October 2025 RES11A-Q1

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. Parameter Measurement Information
    1. 6.1 DC Measurement Configurations
    2. 6.2 AC Measurement Configurations
    3. 6.3 Error Notation and Units
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Ratiometric Matching for Low Gain Error
        1. 7.3.1.1 Absolute and Ratiometric Tolerances
      2. 7.3.2 Ratiometric Drift
        1. 7.3.2.1 Long-Term Stability
      3. 7.3.3 Predictable Voltage Coefficient
      4. 7.3.4 Ultra-Low Noise
    4. 7.4 Device Functional Modes
      1. 7.4.1 Per-Resistor Limitations
  9. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Amplifier Feedback Circuit
        1. 8.1.1.1 Amplifier Feedback Circuit Example
      2. 8.1.2 Voltage Divider Circuit
        1. 8.1.2.1 Voltage Divider Circuit Example
        2. 8.1.2.2 Voltage-Divider Circuit Drift
      3. 8.1.3 Discrete Difference Amplifier
        1. 8.1.3.1 Difference-Amplifier Common-Mode Rejection Analysis
        2. 8.1.3.2 Difference-Amplifier Gain Error Analysis
      4. 8.1.4 Discrete Instrumentation Amplifiers
      5. 8.1.5 Fully Differential Amplifier
      6. 8.1.6 Unconventional Circuits
        1. 8.1.6.1 Single-Channel Voltage Divider
        2. 8.1.6.2 Single-Channel Amplifier Gain
          1. 8.1.6.2.1 Gain Scaling the RES60A-Q1 With the RES11A-Q1
      7. 8.1.7 Unconventional Instrumentation Amplifiers
    2. 8.2 Typical Application
      1. 8.2.1 Common-Mode Shifting Input Stage
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Examples
  10. Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 PSpice® for TI
        2. 9.1.1.2 TINA-TI™ Simulation Software (Free Download)
        3. 9.1.1.3 TI Reference Designs
        4. 9.1.1.4 Analog Filter Designer
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Difference-Amplifier Common-Mode Rejection Analysis

In this simple difference amplifier configuration, the nominal CMRR is calculated as:

Equation 42. CMRR = 20 × log 10 A D A CM

The term AD is the differential gain of the circuit, and the term ACM is the common-mode gain of the circuit. These are defined as the following:

Equation 43. A D × = V OUT V D = 0.5 × R G1 R G1 + R IN1 + R G2 R G2 + R IN2 R IN2 R G2 + R IN2
Equation 44. A C M = V OUT V CM = R G1 R G1 + R IN1 - R G2 R G2 + R IN2 R IN2 R G2 + R IN2

Therefore,

Equation 45. CMRR = 20 × log 10 R G1 × R IN2 + R G2 R G2 × R IN1 + R G1 R G1 × R IN2 + R G2 + R G2 × R IN1 + R G1

When this expression is evaluated with the definitions given in Section 7.3.1, assuming the worst-case scenario of the most unbalanced divider matching possible:

Equation 46. CMRR = 20 × log 10 G nom +1+ t Rx 2 1- G nom t Rx

tRx2 << 1; therefore, the worst-case CMRR is approximated as:

Equation 47. CMRR = 20 × log 10 G nom +1 t Rx

By definition, the parameter tM describes the effective error that is otherwise equivalent to 4 × tx for an unmatched divider network, and so the maximum value of tM can be used to calculate the same worst-case result. Likewise, the typical value of tM can be used to approximate the typical CMRR.

Equation 48. CMRR = 20 × log 10 G nom +1 t M

For example, the worst-case CMRR for a RES11A40-Q1 device with G = 4 is approximately 74.0dB, with a typical CMRR of approximately 98.5dB. In comparison, implementation of a comparable G = 4 difference amplifier with unmatched 0.1%-tolerance resistors results in a worst-case CMRR of approximately 62dB.

In a difference amplifier configuration, the CMRR of the op amp contributes error as well. The op-amp CMRR is considered in parallel with the CMRR of the resistor network, as per the following equation:

Equation 49. 1 CMRR TOTAL = 1 CMRR AMP + 1 CMRR RESISTORS

Additional mismatches in the divider end-to-end resistances reduce the effective CMRR of a difference amplifier. While the low absolute tolerance span of the RES11A-Q1 (65ppm typical) helps reduce these concerns, parasitic trace resistances can lead to additional mismatches that impact the CMRR specs. Bench results from a difference amplifier implementation of the RES11A40-Q1 and the OPA210 are presented for various deliberate input-impedance mismatches.

RES11A-Q1 Effect of Input Impedance
                    Mismatch on Common-mode Rejection Ratio Figure 8-7 Effect of Input Impedance Mismatch on Common-mode Rejection Ratio