SLPS755B October   2023  – October 2025 RES11A-Q1

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. Parameter Measurement Information
    1. 6.1 DC Measurement Configurations
    2. 6.2 AC Measurement Configurations
    3. 6.3 Error Notation and Units
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Ratiometric Matching for Low Gain Error
        1. 7.3.1.1 Absolute and Ratiometric Tolerances
      2. 7.3.2 Ratiometric Drift
        1. 7.3.2.1 Long-Term Stability
      3. 7.3.3 Predictable Voltage Coefficient
      4. 7.3.4 Ultra-Low Noise
    4. 7.4 Device Functional Modes
      1. 7.4.1 Per-Resistor Limitations
  9. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Amplifier Feedback Circuit
        1. 8.1.1.1 Amplifier Feedback Circuit Example
      2. 8.1.2 Voltage Divider Circuit
        1. 8.1.2.1 Voltage Divider Circuit Example
        2. 8.1.2.2 Voltage-Divider Circuit Drift
      3. 8.1.3 Discrete Difference Amplifier
        1. 8.1.3.1 Difference-Amplifier Common-Mode Rejection Analysis
        2. 8.1.3.2 Difference-Amplifier Gain Error Analysis
      4. 8.1.4 Discrete Instrumentation Amplifiers
      5. 8.1.5 Fully Differential Amplifier
      6. 8.1.6 Unconventional Circuits
        1. 8.1.6.1 Single-Channel Voltage Divider
        2. 8.1.6.2 Single-Channel Amplifier Gain
          1. 8.1.6.2.1 Gain Scaling the RES60A-Q1 With the RES11A-Q1
      7. 8.1.7 Unconventional Instrumentation Amplifiers
    2. 8.2 Typical Application
      1. 8.2.1 Common-Mode Shifting Input Stage
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Examples
  10. Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 PSpice® for TI
        2. 9.1.1.2 TINA-TI™ Simulation Software (Free Download)
        3. 9.1.1.3 TI Reference Designs
        4. 9.1.1.4 Analog Filter Designer
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Long-Term Stability

Biased long-term drift testing was performed on the automotive-grade RES11A-Q1 using a temperature-controlled oil bath. The devices under test were first soldered to the bias boards using a reflow oven, per J-STD-020E, then were cleaned in an ultrasonic bath. The boards underwent an additional bake step before placement in the oil bath. The ambient bath temperature was fixed at 46°C and each divider was biased to a fixed voltage of 15V. Devices were allowed to soak for 45 minutes, to achieve thermal equilibrium, before measurements commenced.

An integration circuit was used to measure current through each divider, and thus identify any changes in end-to-end resistance. A delta measurement between the midpoint pins of the dividers provided a high-resolution measurement of divider-to-divider shifts for the same DUT, allowing approximation of shifts in tM. Additional measurements between the midpoints and ground were performed, to be used in conjunction with the previous measurements for calculation of shifts in tDx. The bias voltage was also measured for each channel. These measurements were implemented using multiplexed digital multimeters (DMMs).

RES11A-Q1 RES11A-Q1 Long-term Drift
                    Schematic (Simplified) Figure 7-1 RES11A-Q1 Long-term Drift Schematic (Simplified)

Measurements were recorded at intervals ranging from 15 minutes to 24 hours, with run durations from 1000hrs to 3600hrs. In some instances, measurement data collection was interrupted due to external factors, such as mandatory system updates to the computer used for the measurements. In these instances, the bias voltage and temperature control were not disturbed due to the use of uninterruptible power supply (UPS) backups for the biasing circuitry; there was simply an absence of recorded data from the DMMs. Plots presented are normalized to the respective run mean.

RES11A-Q1 RES11A40-Q1 Long-term
                    Drift, tDFigure 7-2 RES11A40-Q1 Long-term Drift, tD
RES11A-Q1 RES11A40-Q1 Long-term
                    Drift, tMFigure 7-3 RES11A40-Q1 Long-term Drift, tM

Accurate measurement of errors in the single-digit ppm range requires careful consideration of circuit parasitics. Noise sources can easily contaminate or dominate measurements. While external filters at the measurement nodes assist with high-frequency noise, the thermal noise of the filter resistors contributes low-frequency noise, so a series of design and architectural tradeoffs are required. Ongoing development of biasing boards, procedures, and facilities continues to increase the effective resolution of these measurements.

RES11A-Q1 RES11A10-Q1 Long-term
                        Drift, tDFigure 7-4 RES11A10-Q1 Long-term Drift, tD
RES11A-Q1 RES11A00-Q1 Long-term
                        Drift, tDFigure 7-6 RES11A00-Q1 Long-term Drift, tD
RES11A-Q1 RES11A10-Q1 Long-term
                        Drift, tMFigure 7-5 RES11A10-Q1 Long-term Drift, tM