SLUP414 April 2024

4 Clamping Options for a PSFB

A PSFB can achieve soft switching on its primary-side switches and have a clean FET drain-to-source voltage (V_DS) waveform without much voltage ringing. However, the PSFB output rectifier parasitic capacitance will resonate with the inductance in series with the transformer windings and lead to high rectifier voltage stress.

Consider the PSFB with a full-bridge synchronous rectifier in Figure 18. The synchronous rectifier V_DS voltage will have large ringing, with the FET output capacitance modeled as shown in Figure 19. The peak value of the ringing could be as high as 2V_IN × N_S/N_P. In order to reduce the rectifier voltage stress and thus use lower drain-to-source on-resistance (R_DS(on)) FETs for better efficiency, you might need to clamp the rectifier voltage stress. One option is to apply a passive clamp circuit to absorb partial energy in the voltage ringing. Figure 20 shows a passive clamp option applied to a PSFB. Figure 21 shows how the addition of a resistor-capacitor diode at the output stage greatly reduces the rectifier voltage stress. The capacitance of the clamping capacitor (C_cl) needs to be large enough to be treated as an ideal voltage source in order to effectively clamp the rectifier voltage stress. C_cl is charged by the clamping diode and dissipates its energy on R_cl. Equation 4 calculates the clamping resistor (R_cl) resistance required to clamp the rectifier voltage at the targeted clamp voltage level (V_CP):

Equation 4.

R_{c l} = \frac{(V_{C P} - V_{O U T}) \times (V_{C P} - V_{d})}{C_{c l} {\times V}_{C P \times} ({2 V}_{d} - V_{C P}) \times f_{S W}}

where V_d = V_IN × N_S/N_P and f_SW is the PSFB switching frequency.

Equation 5 calculates the power dissipation on the clamping resistor as:

Equation 5.

P_{R_{c l}} = \frac{{(V_{C P} - V_{O U T})}^{2}}{R_{c l}}

As Equation 4 and Equation 5 illustrate, a lower V_CP requires lower R_cl and higher power dissipation on R_cl.

Figure 18 A PSFB with a synchronous rectifier.

Figure 19 Waveforms of a PSFB without voltage clamping on the output rectifier.

Figure 20 A PSFB with a passive clamp.

Figure 21 Waveforms (with solid lines) of a PSFB with a passive clamp circuit.

A PSFB relies on energy stored in the inductor in series with the transformer winding to achieve soft switching. But the inductor will resonate with the rectifier parasitic capacitors, resulting in high rectifier voltage stress. If you can reduce the inductance of the transformer series inductor, you can reduce the rectifier voltage stress. A primary clamp, shown in Figure 22, can enable the use of a smaller series inductor by adding two diodes, with the transformer series inductor placed between the half-bridge FET leg and the clamping diodes. By doing so, the only transformer series inductor will be the transformer leakage inductor.

Figure 23 shows waveforms of a PSFB both with and without a primary clamp. L_S is set to 3.5 µH and the leakage inductance (L_lk) is set to 0.5 µH. With the diode clamp at the primary side, it is possible to recycle the energy in L_S and keep it at the primary side. The output rectifier parasitic capacitor will only resonate with L_lk, reducing output rectifier voltage stress significantly. Because you need the discrete inductor L_S in a PSFB with a primary clamp to maintain soft switching with a small L_lk, the power density might be lower than a PSFB with another clamping method.

Figure 22 A PSFB with a primary clamp.

Figure 23 Waveforms of a PSFB both with (solid lines) and without (dashed lines) a primary clamp circuit.

Instead of burning power on a clamp resistor such as a passive clamp or adding a discrete inductor such as a primary clamp, using the active clamp shown in Figure 24 could help optimize both size and efficiency. An active clamp leg (ACL) formed by a capacitor (C_CL) and a MOSFET (Q_CL) is inserted before the output inductor. When the output winding voltage becomes nonzero, energy will transfer from the primary winding to the secondary winding to energize the output inductor and also conduct current through the Q_CL body diode to charge C_CL, even if Q_CL is not turned on. Turning on Q_CL after its body has already conducted current will ensure zero voltage switching (ZVS) on Q_CL. It is important to turn on Q_CL before the current polarity change in order to allow the completion of the current-second balance (or charge balance) on C_CL at the beginning of D_effT_S.

Figure 25 shows that there is a nonmonotonic current on the synchronous rectifier current as well as the transformer winding current, which could pose challenges for peak current-mode control, since peak current-mode control generally requires a monotonic current rise on transformer current during the effective duty-cycle period. Q_CL only needs to be turned on long enough for the active clamp current-second balance to work as intended – to clamp the output rectifier voltage to the C_CL voltage (V_CL). Q_CL doesn’t need to conduct throughout the full D_effT_S, but for a relatively short period of time instead.

Therefore, we propose setting Q_CL to have a fixed-on time (D_ACLT_S = constant) while keeping D_effT_S always greater than the duration where the current-second balance is completed (D_CSBT_S) under whole operational voltage and load ranges. Since D_effT_S is larger than D_CSBT_S, peak current detection will always occur when the transformer current rises monotonically. The PSFB is generally designed to have a larger D_eff at mid to heavy loads, where D_eff >> D_CSB is expected. At light loads, the converter usually operates under discontinuous conduction mode, where D_eff will be smaller than D_eff under continuous conduction mode at the same input/output voltage condition.

In order to keep D_effT_S greater than D_CSBT_S even at light loads, you can implement frequency reduction control or burst operation. It is important to turn on Q_CL only after the duty-cycle loss period has ended; otherwise, the energy stored in C_CL will dump back to the primary side, overstress the synchronous rectifier, and potentially damage the components. C_CL needs to be large enough to be treated as an ideal voltage source to effectively reduce the synchronous rectifier voltage stress. Therefore, you must ensure that C_CL selection meets the inequality expressed by Equation 6:

Equation 6.

T_{S} ≪ 2 π \sqrt{{(\frac{N_{S}}{N_{P}})}^{2} L_{S} C_{C L}}

Assuming zero voltage ripple on C_CL, it is possible to clamp the rectifier voltage to V_INN_S/N_P, which is half the voltage stress without any clamp circuit. The active clamp doesn’t dissipate the ringing energy on the power resistor but circulates the energy in the LC resonant tank as a lossless snubber. Therefore, you can expect higher converter efficiency on a PSFB with an active clamp than on a PSFB with a passive clamp in an identical specification.

The synchronous rectifier C_oss will control the peak current on the ACL. Selecting a low C_oss synchronous rectifier FET will mean a lower ACL root-mean-square (RMS) current and thus help improve converter efficiency.

Here are some design guidelines when designing a PSFB with an active clamp:

Q_CL must turn on only after a duty-cycle loss duration to avoid C_CL energy backflow to the primary side.
Q_CL must turn on while the body diode is still conducting current for ZVS.
A longer Q_CL on-time will reduce V_CL as well as synchronous rectifier voltage stress, but the Q_CL RMS current will increase.
A lower synchronous rectifier C_oss not only helps reduce ACL RMS current, but also helps reduce synchronous rectifier voltage stress.

Figure 24 A PSFB with an active clamp.

Figure 25 Waveforms of a PSFB with an active clamp.