2 PSFB Operational Principles

Figure 9 shows a full-bridge converter with a diode rectifier, while Figure 10 shows full-bridge converter waveforms under phase-shifted control, which allows a negative drain-to-source current before the MOSFET turns on transients for soft switching. As shown in Figure 10, a phase difference is created between leg 1 MOSFET driving signals (Out1L and Out1H) and leg 2 MOSFET driving signals (Out2L and Out2H), while all four driving signals keep their duty cycle unchanged. When a diagonal pair of MOSFETs turn on, either the input voltage (+V_IN) or inversed input voltage (–V_IN) is applied to V_AB, which is the time between the energizing of the series inductor (L_S) and the delivery of energy from the input side (the primary side) to the output side (the secondary side) through the transformer. The phase difference between leg 1 and leg 2 determines the nonzero voltage duration (pulse width) of V_AB. A bipolar square wave similar to the V_AB waveform is generated at the secondary voltage (V_SEC), which will be further rectified by the output diode rectifier to become a unipolar square wave, thus allowing the output inductor to perform “buck” operation for output regulation controlled by the V_SEC pulse width.

The pulse width of V_SEC is smaller than V_AB because L_S uses the applied V_IN to switch its current polarity, resulting in zero voltage on the transformer winding and thus a smaller V_SEC pulse width, which is known as the duty-cycle loss. The larger the L_S inductance, the larger the duty-cycle loss (the difference of pulse widths between V_AB and V_SEC). Enabling a larger D_eff on the secondary side for a wider duty-cycle variation range requires the use of a smaller L_S inductance.

Energy stored in L_S during switching transients is the key to realizing soft switching at the primary-side MOSFETs. A small L_S inductance means less energy stored, which could be insufficient to discharge the MOSFET output capacitor voltage for soft switching, especially at light loads. Thus, you must make a trade-off between soft switching and the D_eff ranges in your design.

Because phase-shifted control enables the primary winding current to continuously circulate and freely flow through the primary full-bridge MOSFETs’ C_oss and body diodes, there may be current lagging on the MOSFETs with inductive impedance at the output of the full-bridge switch nodes and negative current at the MOSFET switching transients, as shown previously in Figure 8. Energy stored in L_S is the key to soft switching, but output inductor L_O also affects soft-switching capability.

Let’s look at the waveform of MOSFET switching transients. The dashed purple curve in Figure 11 is the leg 1 high-side MOSFET current. Notice that the leg 1 low-side MOSFET current is identical to the leg 1 high-side MOSFET current but happens at the leg 1 high-side MOSFET turnoff period. You can see that the primary current (I_PRI) level at the MOSFET turnon transient is at the L_O current ripple valley point. In other words, leg 1 MOSFET’s soft-switching capability will drop if the L_O current ripple is large (that is, if the L_O inductance is smaller). Assuming that the transformer magnetizing inductor current is zero, Equation 2 expresses the current used to achieve soft switching at the leg 1 MOSFETs as:

where I_LO,pp is the peak-to-peak current ripple on L_O.

Equation 3 calculates the current used to achieve soft switching at leg 2 MOSFETs as:

Figure 12 highlights the leg 2 low-side MOSFET current with a dashed black line. Notice that the leg 2 high-side MOSFET current is identical to the leg 2 low-side MOSFET current, but happens at the leg 2 low-side MOSFET turnoff period. From Equation 2 and Equation 3, as well as the waveforms in Figure 11 and Figure 12, you can see that it is easier to achieve soft switching for MOSFETs on leg 2 than on leg 1.