8 PSFB Design Example

To verify performance, we built a 54-V, 3-kW PSFB with an active clamp reference design targeting the M-CRPS specification. Figure 39 and Figure 40 show the block diagram and board photo of this reference design, respectively. The reference design uses the TMDSCNCD280039C C2000™ microcontroller for PSFB control, gallium nitride FETs for efficiency optimization, and a current transformer on the primary winding for peak current-mode control current sensing. The total power-stage dimensions are 100 mm by 65 mm by 40 mm. Figure 41 shows steady-state waveforms at a 3-kW load. The active clamp MOSFET is programmed to turn on for only 300 nS with a 140-kHz PSFB switching frequency, therefore limiting the nonmonotonic I_PRI duration to less than 1 µS and allowing a wide D_eff range. The transformer secondary winding voltage (V_SEC) peak represents synchronous rectifier FET voltage stress. Figure 41 also shows the 80-V voltage stress on the synchronous rectifier FETs with a 54-V output, enabling us to use 100-V rated synchronous rectifier FETs. Figure 42 shows a 50% load transient with a 1-A/µS current-changing slew rate. This reference design demonstrates much better performance than M-CRPS limits.