5 PSFB Control

This section introduces some of the nuances concerning the control of a PSFB. Figure 26 is a high-level block diagram of the control logic needed to implement a PSFB, where OUT1H and OUT1L are the gate logic for one half bridge of the primary FETs and OUT2H and OUT2L are the gate logic of the other half bridge of the primary FETs. A clock set to the intended switching frequency directly controls the OUT1H and OUT1L PWM pair. The OUT2H and OUT2L are controlled by a combination of:

• A ramp signal consisting of a resistor, capacitor and a fixed reference voltage, V_{RAMP_REF}.
• An error amplifier that samples the output voltage through a resistor divider with a compensation network.
• A comparator that compares the output of the error amplifier and the ramp signal voltage.
• A T flip-flop that sets the state of OUT2H and OUT2L based on the comparator output. The T flip-flop is rising edge-trigged.

Figure 27 illustrates the gate-logic waveforms of the circuit shown in Figure 26. At the beginning of a new switching cycle, the ramp signal resets to 0 V and the diagonal pair of primary FETs, OUT1H and OUT2L, turn on. When the ramp signal, V_RAMP, becomes larger than the error amplifier output voltage, V_COMP, the T flip-flop toggles, changing the state of OUT2H and OUT2L. At the halfway point of the switching period, the state of OUT1H and OUT1L changes and the ramp voltage resets. The other diagonal pair of primary FETs, OUT1L and OUT2H, are now on. When the ramp signal exceeds the error amplifier output voltage, the T flip-flop toggles again, changing the state of OUT2H and OUT2L.

The control logic we’ve just described is known as voltage-mode control. Figure 28 shows a slight variation of this control logic, which uses V_IN or a voltage proportional to V_IN instead of a fixed reference voltage to generate the ramp signal. The advantage of this method is that the control logic instantly reflects changes in V_IN, as the transient voltage (dV/dt) of the ramp immediately changes with V_IN. This minimizes deviations of V_OUT caused by changes in V_IN.

Figure 29 shows another variation of the control logic known as peak current-mode control. This method replaces the ramp signal with sampled current information, I_CS, from the power stage.

The decision to use voltage-mode control or peak current-mode control has ramifications for the design of the power stage of the PSFB. For voltage-mode control, you would need to place a DC blocking capacitor in series with the transformer primary winding, as shown in Figure 30, in order to avoid the transformer saturation issue caused by the winding current imbalance. Because all of the transformer primary winding current flows through the DC blocking capacitor, you will need a sufficient current rating capacitor or a combination of capacitors that satisfy the required current rating. The voltage stress of the rectifiers on the secondary side increases when applying the DC blocking capacitor. That is because the DC blocking capacitor voltage ripple makes the transformer primary winding voltage amplitude greater than V_IN when a diagonal pair of primary MOSFETs turns on. Therefore, you must make a trade-off between the size and capacitance of the DC blocking capacitor and the voltage stress.

One of the benefits of current-mode control is that the DC blocking capacitor is not required, as the control loop directly samples and regulates the peak current of the transformer. Figure 31 circles three locations where it is possible to implement power-stage current sampling.

Location No. 1 places a current-sensing element such as a current-sense transformer in series with the PSFB transformer. One of the benefits of this location is that you can automatically reset the current-sense transformer core because of the bidirectional current flow of the PSFB transformer. One of the disadvantages of this location is that the current-sense signal from the transformer only contains AC information but not DC information. Items such as delay mismatches in the power stage or common-mode noise coupling into the current-sense signal can bias the PSFB transformer current to one side, potentially requiring a larger margin on the transformer design to avoid saturation.

Location No. 2 places the current sampling between the input capacitor and the full bridge on the primary. You can place a transformer between the input capacitor and the full bridge or in the return path from the full bridge going back to the input capacitor. The benefit of this location is that the current-sense signal of the transformer contains both AC and DC information and avoids the disadvantages of location No. 1. The drawback of location No. 2 is an increase in the parasitic inductance within the primary-side power-stage loop. It is important to manage the voltage stress on the primary FETs caused by ringing coming from higher parasitic loop inductance. Another challenge of this location is the need to reset the transformer core twice every switching cycle. This reset occurs when both high-side or both low-side primary FETs are on. The transformer core reset becomes even more challenging for designs requiring a high duty cycle or high-frequency designs where the amount of time to complete the reset is smaller. It is also possible to use a shunt resistor plus a current sense amplifier as a current-sensing element in the return path from the full bridge going back to the input capacitor. This avoids any transformer reset challenges, with the trade-off of power dissipation in the shunt resistor.

Location No. 3 is on the secondary side in the return path of the output inductor current going back to the rectifiers. Designers often use a current-sense resistor and current-sense amplifier for this location. Unlike the other two locations, the current sampling is located on the converter’s secondary side, which can simplify the implementation if the PSFB controller is also located on the secondary side, since there is no need to cross the isolation barrier. Among the three locations, when applying active clamping, location No. 3 is the only location that doesn’t have distorted current during the current ramping period.

Figure 32 compares the plant transfer function of the voltage mode-controlled PSFB model presented by Christophe Basso in “Transfer Functions of Switching Converters” and the plant transfer function of the peak current mode-controlled PSFB model presented by Shi-Song Wang in “Small-Signal Modeling of Phase-Shift Full-Bridge Converter with Peak Current Mode Control” for a 3-kW, 400-V_IN to 12-V_OUT PSFB converter operating at 100 kHz. The PSFB is a buck-derived topology, and while you may expect similarities between the voltage mode-controlled buck and the voltage mode-controlled PSFB, the impact of duty-cycle loss caused by L_S results in a damping effect, such that there is an absence of peaking in the AC response of the voltage mode-controlled PSFB. The voltage mode-controlled model presents two real poles in its plant transfer function, while the peak current mode-controlled model presents one real pole. The softer rolloff of the gain in peak current-mode control suggests that it has an advantage because it achieves a higher loop bandwidth, which is appealing for applications where load transient response is a concern.