SLUS756D September   2007  – June 2026 BQ24751A

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
    1. 4.1 Terminal Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Package Thermal Data
    4. 5.4 Electrical Characteristics
    5. 5.5 Typical Charateristics
  7. 6 Detailed Description
    1. 6.1  Functional Block Diagram
    2. 6.2  Battery Voltage Regulation
    3. 6.3  Battery Current Regulation
    4. 6.4  Input Adapter Current Regulation
    5. 6.5  Adapter Detect and Power Up
    6. 6.6  Enable and Disable Charging
    7. 6.7  System Power Selector
    8. 6.8  Battery Learn Cycles
    9. 6.9  Automatic Internal Soft-Start Charger Current
    10. 6.10 Converter Operation
    11. 6.11 Synchronous and Non-Synchronous Operation
    12. 6.12 High Accuracy IADAPT Using Current Sense Amplifier (CSA)
    13. 6.13 Input Overvoltage Protection (ACOV)
    14. 6.14 Input Undervoltage Lock Out (UVLO)
    15. 6.15 Battery Overvoltage Protection
    16. 6.16 Battery Shorted (Battery Undervoltage) Protection
    17. 6.17 Charge Overcurrent Protection
    18. 6.18 Thermal Shutdown Protection
    19. 6.19 Adapter Detected Status Register ( ACGOOD Pin)
    20. 6.20 Input Over-Power Protection (ACOP)
      1. 6.20.1 Conditions for ACOP Latch Off:
  8. 7 Application Information
    1. 7.1 Input Capacitance Calculation
    2. 7.2 PCB Layout Design Guideline
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.4 Electrical Characteristics

7.0 V ≤ VPVCC ≤ 24 V, 0°C < TJ < +125°C, typical values are at TA = 25°C, with respect to AGND (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OPERATING CONDITIONS
VPVCC_OP PVCC Input voltage operating range 5.0 24.0 V
CHARGE VOLTAGE REGULATION
VBAT_REG_RNG BAT voltage regulation range 4-4.512 V per cell, times 2,3,4 cells 8 18.048 V
VVDAC_OP VDAC reference voltage range 2.6 3.6 V
VADJ_OP VADJ voltage range 0 REGN V
Charge voltage regulation accuracy 8 V, 8.4 V, 9.024 V –0.5 0.5 %
12 V, 12.6 V, 13.536 V –0.5 0.5
16 V, 16.8 V, 18.048 V –0.5 0.5
Charge voltage regulation set to default to 4.2 V per cell VADJ connected to REGN, 8.4 V, 12.6 V, 16.8 V –0.5 0.5 %
CHARGE CURRENT REGULATION
VIREG_CHG Charge current regulation differential voltage range VIREG_CHG = VSRP – VSRN 0 100 mV
VSRSET_OP SRSET voltage range 0 VDAC V
Charge current regulation accuracy VIREG_CHG = 40–100 mV –3 3 %
VIREG_CHG = 20 mV –5 5
VIREG_CHG = 5 mV –25 25
VIREG_CHG = 1.5 mV (VBAT>4V) –33 33
INPUT CURRENT REGULATION
VIREG_DPM Adapter current regulation differential voltage range VIREG_DPM = VACP – VACN 0 100 mV
VACSET_OP ACSET voltage range 0 VDAC V
Input current regulation accuracy VIREG_DPM = 40–100 mV –3 3 %
VIREG_DPM = 20 mV –5 5
VIREG_DPM = 5 mV –25 25
VIREG_DPM = 1.5 mV –33 33
VREF REGULATOR
VVREF_REG VREF regulator voltage VACDET > 0.6 V, 0-30 mA 3.267 3.3 3.333 V
IVREF_LIM VREF current limit VVREF = 0 V, VACDET > 0.6 V 35 75 mA
REGN REGULATOR
VREGN_REG REGN regulator voltage VACDET > 0.6 V, 0-75 mA, PVCC > 10 V 5.6 5.9 6.2 V
IREGN_LIM REGN current limit VREGN = 0 V, VACDET > 0.6 V 90 135 mA
ADAPTER CURRENT SENSE AMPLIFIER
VACP/N_OP Input common mode range Voltage on ACP/ACN 0 24 V
VIADAPT IADAPT output voltage range 0 2
IIADAPT IADAPT output current 0 1 mA
AIADAPT Current sense amplifier voltage gain AIADAPT = VIADAPT / VIREG_DPM 20 V/V
Adapter current sense accuracy VIREG_DPM = 40–100 mV –2 2 %
VIREG_DPM = 20 mV –3 3
VIREG_DPM = 5 mV –25 25
VIREG_DPM = 1.5 mV –33 33
IIADAPT_LIM Output current limit VIADAPT = 0 V 1 mA
CIADAPT_MAX Maximum output load capacitance For stability with 0 mA to 1 mA load 100 pF
ACDET COMPARATOR
VACDET_CHG ACDET adapter-detect rising threshold Min voltage to enable charging, VACDET rising 2.376 2.40 2.424 V
VACDET_CHG_HYS ACDET falling hysteresis VACDET falling 40 mV
ACDET rising deglitch VACDET rising 518 700 908 ms
ACDET falling deglitch VACDET falling 7 9 11 ms
VACDET_BIAS ACDET enable-bias rising threshold Min voltage to enable all bias, VACDET rising 0.56 0.62 0.68 V
VACDET_BIAS_HYS Adapter present falling hysteresis VACDET falling 20 mV
ACDET rising deglitch VACDET rising 10 μs
ACDET falling deglitch VACDET falling 10 μs
PVCC / BAT COMPARATOR (REVERSE DISCHARGING PROTECTION)
VPVCC-BAT_OP Differential Voltage from PVCC to BAT –20 24 V
VPVCC-BAT_FALL PVCC to BAT falling threshold VPVCC – VBAT to turn off ACFET 140 185 240 mV
VPVCC-BAT__HYS PVCC to BAT hysteresis 50 mV
PVCC to BAT Rising Deglitch VPVCC – VBAT > VPVCC-BAT_RISE 7 9 11 ms
PVCC to BAT Falling Deglitch VPVCC – VBAT < VPVCC-BAT_FALL 6 μs
INPUT UNDERVOLTAGE LOCK-OUT COMPARATOR (UVLO)
VUVLO AC Under-voltage rising threshold Measured on PVCC 3.5 4 4.5 V
VUVLO_HYS AC Under-voltage hysteresis, falling 260 mV
ACN / BAT COMPARATOR
VACN-BAT_FALL ACN to BAT falling threshold VACN – VBAT to turn on BATDRV 175 285 340 mV
VACN-BAT_HYS ACN to BAT hysteresis 50 mV
ACN to BAT rising deglitch VACN – VBAT > VACN-BAT_RISE 20 μs
ACN to BAT falling deglitch VACN – VBAT < VACN-BAT_FALL 6 μs
BAT OVERVOLTAGE COMPARATOR
VOV_RISE Overvoltage rising threshold As percentage of VBAT_REG 104 %
VOV_FALL Overvoltage falling threshold As percentage of VBAT_REG 102
BAT SHORT (UNDERVOLTAGE) COMPARATOR
VBAT_SHORT_FALL BAT short falling threshold 2.755 2.9 3.045 V/cell
VBAT_SHORT_HYS BAT short hysteresis 250 mV/cell
BAT short rising deglitch VBAT > VBAT_SHORT+VBAT_SHORT_HYS
Detection delay		 1.5 s
BAT short falling deglitch VBAT < VBAT_SHORT 1.5
CHARGE OVERCURRENT COMPARATOR
VOC Charge over-current falling threshold As percentage of IREG_CHG 145 %
Minimum Current Limit (SRP-SRN) 50 mV
CHARGE UNDERCURRENT COMPARATOR (SYNCHRONOUS TO NON-SYNCHRONOUS TRANSITION)
VISYNSET_FALL Charge undercurrent falling threshold Changing from synchronous to non-sysnchronous 9.75 13 16.25 mV
VISYNSET_HYS Charge undercurrent rising hysteresis 8 mV
Charge undercurrent, falling-current deglitch VIREG_DPM < VISYNSET 20 μs
Charge undercurrent, rising-current deglitch 640
INPUT OVER-POWER COMPARATOR (ACOP)
VACOC ACOC Gain for initial ACOC current limit limit (Percentage of programmed VIREG_DPM) Begins 700 ms after ACDET
Input current limited to this threshold for fault protection		 150 %
VIREG_DPM
VACOC_CEILING Maximum ACOC input current limit (VACP–VACN)max Internally limited ceiling
VACOC_MAX = (VACP–VACN)max		 100 mV
ACOP Latch Blankout Time with ACOC active
(begins 700 ms after ACDET)		 Begins 700 ms after ACDET
(does not allow ACOP latch-off, and no ACOP source current)		 2 ms
VACOP ACOP pin latch-off threshold voltage
(See ACOP in Terminal Functions table )		 1.95 2 2.05 V
KACOP Gain for ACOP Source Current when in ACOC Current source on when in ACOC limit. Function of voltage across power FET
IACOP_SOURCE = KACOP ×(VPVCC -VACP)		 18 μA / V
IACOP_SINK ACOP Sink Current when not in ACOC
ACOP Latch is reset by going below ACDET or UVLO		 Current sink on when not in ACOC 5 μA
VACN-SHORT ACN Short protection threshold latching ACN < 2.4 V, ACDET > 2.4 V 2.4 V
INPUT OVERVOLTAGE COMPARATOR (ACOV)
VACOV AC Overvoltage rising threshold on OVPSET
(See OVPSET in Section 4.1 )		 Measured on OVPSET 3.007 3.1 3.193 V
VACOV_HYS AC Over-voltage rising deglitch 1.3 ms
AC Over-voltage falling deglitch 1.3
THERMAL SHUTDOWN COMPARATOR
TSHUT Thermal shutdown rising temperature Temperature Increasing 155 °C
TSHUT_HYS Thermal shutdown hysteresis, falling 20 °C
BATTERY SWITCH ( BATDRV) DRIVER
RDS_BAT_OFF BATFET Turn-off resistance VACN > 5 V 160 Ω
RDS_BAT_ON BATFET Turn-on resistance VACN > 5 V 3 kΩ
VBATDRV_REG BATFET drive voltage VBATDRV_REG = VACN – VBATDRV when
VACN > 5 V and BATFET is on		 6.5 V
BATFET Power-up delay Delay to turn off BATFET after adapter is detected (after ACDET > 2.4) 518 700 908 ms
AC SWITCH ( ACDRV) DRIVER
RDS_AC_OFF ACFET turn-off resistance VPVCC > 5 V 80 Ω
RDS_AC_ON ACFET turn-on resistance VPVCC > 5 V 2.5 kΩ
VACDRV_REG ACFET drive voltage VACDRV_REG = VPVCC – VACDRV when
VPVCC > 5 V and ACFET is on		 6.5 V
ACFET Power-up Delay Delay to turn on ACFET after adapter is detected (after ACDET > 2.4) 518 700 908 ms
AC / BAT MOSFET DRIVERS TIMING
Driver dead time Dead time when switching between ACDRV and BATDRV 10 μs
PWM HIGH SIDE DRIVER (HIDRV)
RDS_HI_ON High side driver turn-on resistance VBTST – VPH = 5.5 V, tested at 100 mA 3 6 Ω
RDS_HI_OFF High side driver turn-off resistance VBTST – VPH = 5.5 V, tested at 100 mA 0.7 1.4 Ω
VBTST_REFRESH Bootstrap refresh comparator threshold voltage VBTST – VPH when low side refresh pulse is requested 4 V
PWM LOW SIDE DRIVER (LODRV)
RDS_LO_ON Low side driver turn-on resistance REGN = 6 V, tested at 100 mA 3 6 Ω
RDS_LO_OFF Low side driver turn-off resistance REGN = 6 V, tested at 100 mA 0.6 1.2 Ω
PWM DRIVERS TIMING
Driver Dead Time — Dead time when switching between LODRV and HIDRV. No load at LODRV and HIDRV 30 ns
PWM OSCILLATOR
FSW PWM switching frequency 240 360 kHz
VRAMP_HEIGHT PWM ramp height As percentage of PVCC 6.6 %PVCC
QUIESCENT CURRENT
IOFF_STATE Total off-state quiescent current into pins SRP, SRN, BAT, BTST, PH, PVCC, ACP, ACN VBAT = 16.8 V, VACDET < 0.6 V,
VPVCC > 5 V, TJ = 0 to 85°C		 7 10 μA
IBATQ_CD Total quiescent current into pins: SRP, SRN, BAT, BTST, PH Adapter present, VACDET > 2.4 V, charge disabled 100 200 μA
IAC Adapter quiescent current VPVCC = 20 V, charge disabled 1 1.5 mA
INTERNAL SOFT START (8 steps to regulation current)
Soft start steps 8 step
Soft start step time 1.7 ms
CHARGER SECTION POWER-UP SEQUENCING
Charge-enable delay after power-up Delay from when adapter is detected to when the charger is allowed to turn on 518 700 908 ms
LOGIC INPUT PIN CHARACTERISTICS ( CHGEN, LEARN)
VIN_LO Input low threshold voltage 0.8 V
VIN_HI Input high threshold voltage 2.1
IBIAS Input bias current VCHGEN = 0 to VREGN 1 μA
tCHGEN_DEGLITCH Charge enable deglitch time, CHGEN falling = enabling charge ACDET > 2.4 V, CHGEN rising 2 ms
LOGIC INPUT PIN CHARACTERISTICS (CELLS)
VIN_LO Input low threshold voltage, 3 cells CELLS voltage falling edge 0.5 V
VIN_MID Input mid threshold voltage, 2 cells CELLS voltage rising for MIN,
CELLS voltage falling for MAX		 0.8 1.8
VIN_HI Input high threshold voltage, 4 cells CELLS voltage rising 2.5
IBIAS_FLOAT Input bias float current for 2-cell selection VCHGEN = 0 to VREGN –1 1 μA
OPEN-DRAIN LOGIC OUTPUT PIN CHARACTERISTICS ( ACGOOD)
VOUT_LO Output low saturation voltage Sink Current = 5 mA 0.5 V
518 700 908 ms
Delay, ACGOOD rising 10 ms
Delay, ACGOOD falling ms