SLUSAM9E July 2011 – April 2020 BQ76925
PRODUCTION DATA.
PARAMETERS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|
DC PARAMETERS | ||||||
VIL | Input Low Logic Threshold | 0.6 | V | |||
VIH | Input High Logic Threshold | 2.8 | V | |||
VOL | Output Low Logic Drive | IOL = 1 mA | 0.20 | V | ||
IOL = 2.5 mA | 0.40 | |||||
VOH | Output High Logic Drive (Not applicable due to open-drain outputs) | N/A | V | |||
ILKG | I2C Pin Leakage | Pin = 5 V, Output in Hi-Z | < 1 | µA | ||
AC PARAMETERS | ||||||
tr | SCL, SDA Rise Time | 1000 | ns | |||
tf | SCL, SDA Fall Time | 300 | ns | |||
tw(H) | SCL Pulse Width High | 4 | µs | |||
tw(L) | SCL Pulse Width Low | 4.7 | µs | |||
tsu(STA) | Setup time for START condition | 4.7 | µs | |||
th(STA) | START condition hold time after which first clock pulse is generated | 4 | µs | |||
tsu(DAT) | Data setup time | 250 | ns | |||
th(DAT) | Data hold time | 0(1) | µs | |||
tsu(STOP) | Setup time for STOP condition | 4 | µs | |||
tsu(BUF) | Time the bus must be free before new transmission can start | 4.7 | µs | |||
t V | Clock Low to Data Out Valid | 900 | ns | |||
th(CH) | Data Out Hold Time After Clock Low | 0 | ns | |||
fSCL | Clock Frequency | 0 | 100 | kHz | ||
tWAKE | I2C ready after transition to Wake Mode | 2.5 | ms |