SLUSEE5 Data sheet

SLUSEE5E January 2022 – April 2026 TPS4811-Q1

PRODUCTION DATA

8.3.2.1 FET Gate Slew Rate Control

For limiting inrush current during turn ON of the FET with capacitive loads, use R₁, R₂, and C₁, as shown in Figure 8-6. The R₁ and C₁ components slow down the voltage ramp rate at the gate of the FET. The FET source follows the gate voltage resulting in a controlled voltage ramp across the output capacitors.

TPS4811-Q1 Inrush Current Limiting with
FET Gate Slew Rate Control

Figure 8-6 Inrush Current Limiting with FET Gate Slew Rate Control

Use the Equation 2 to calculate the inrush current during turn-ON of the FET.

Equation 2.

I_{I N R U S H} = C_{L O A D} \times \frac{V_{B A T T}}{T_{c h a r g e}}

Equation 3.

I_{I N R U S H} = \frac{0.63 \times V_{(B S T - S R C)} \times C_{L O A D}}{R_{1} \times C_{1}}

Where

C_LOAD is the load capacitance
VBATT is the input voltage
T_charge is the charge time
V_(BST-SRC) is the charge pump voltage (12V)

Use a damping resistor R₂ (≅ 10Ω) in series with C₁. Equation 3 can be used to compute required C₁ value for a target inrush current. A 100kΩ resistor for R₁ can be a good starting point for calculations.

Connecting PD pin of TPS4811x-Q1 directly to the gate of the external FET ensures fast turn OFF without any impact of R₁ and C₁ components.

C₁ results in an additional loading on C_BST to charge during turn ON. Use Equation 4 to calculate the required C_BST value.

Equation 4.

C_{B S T} > Q_{g (t o t a l)} + 10 \times C_{1}

Where, Q_g(total) is the total gate charge of the FET.