SLUSEE5E January   2022  – April 2026 TPS4811-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Recommended Operating Conditions
    3. 6.3 ESD Ratings
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Charge Pump and Gate Driver output (VS, PU, PD, BST, SRC)
      2. 8.3.2 Capacitive Load Driving
        1. 8.3.2.1 FET Gate Slew Rate Control
        2. 8.3.2.2 Using Precharge FET - (with TPS48111Q1 Only)
      3. 8.3.3 Overcurrent and Short-Circuit Protection
        1. 8.3.3.1 Overcurrent Protection With Auto-Retry
        2. 8.3.3.2 Overcurrent Protection With Latch-Off
        3. 8.3.3.3 Short-Circuit Protection
      4. 8.3.4 Analog Current Monitor Output (IMON)
      5. 8.3.5 Overvoltage (OV) and Undervoltage Protection (UVLO)
      6. 8.3.6 Remote Temperature sensing and Protection (DIODE)
      7. 8.3.7 Output Reverse Polarity Protection
      8. 8.3.8 TPS4811x-Q1 as a Simple Gate Driver
    4. 8.4 Device Functional Mode (Shutdown Mode)
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application: Driving HVAC PTC Heater Load on KL40 Line in Power Distribution Unit
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Selection of Current Sense Resistor, RSNS
        2. 9.2.2.2 Selection of Scaling Resistor, RSET
        3. 9.2.2.3 Programming the Overcurrent Protection Threshold - RIWRN Selection
        4. 9.2.2.4 Programming the Short-Circuit Protection Threshold - RISCP Selection
        5. 9.2.2.5 Programming the Fault Timer Period - CTMR Selection
        6. 9.2.2.6 Selection of MOSFET, Q1
        7. 9.2.2.7 Selection of Bootstrap Capacitor, CBST
        8. 9.2.2.8 Setting the Undervoltage Lockout and Overvoltage Set Point
        9. 9.2.2.9 Choosing the Current Monitoring Resistor, RIMON
      3. 9.2.3 Application Curves
    3. 9.3 Typical Application: Driving B2B FETs With Pre-Charging the Output Capacitance
      1. 9.3.1 Design Requirements
      2. 9.3.2 External Component Selection
        1. 9.3.2.1 Selection of Pre-Charge Resistor
      3. 9.3.3 Application Curves
    4. 9.4 Typical Application: Designing for EMI
      1. 9.4.1 Common EMI Components
      2. 9.4.2 Programming the Overcurrent Protection Threshold with Added DC Resistance - RIWRN
      3. 9.4.3 Choosing the Current Monitoring Resistor with Added DC Resistance - RIMON
      4. 9.4.4 Programming the Short Circuit Protection Threshold with Added DC Resistance - RISCP
    5. 9.5 Power Supply and EMI Recommendations
    6. 9.6 Layout
      1. 9.6.1 Layout Guidelines
      2. 9.6.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

8.3.2.2 Using Precharge FET - (with TPS48111Q1 Only)

In high-current applications where several FETs are connected in parallel, the gate slew rate control for the main FETs is not recommended due to unequal distribution of inrush currents among the FETs. This action makes FET selection complex and results in over sizing of the FETs.

The TPS48111Q1 integrates precharge gate driver (G) with a dedicated control input (INP_G). This feature can be used to drive a separate FET that can be used to precharge the capacitive load. Figure 8-7 shows the precharge FET implementation for capacitive load charging using TPS48111Q1. An external capacitor Cg reduces the gate turn-ON slew rate and controls the inrush current.

TPS4811-Q1 Capacitor Charging Using Gate Slew Rate Control of Precharge FET Figure 8-7 Capacitor Charging Using Gate Slew Rate Control of Precharge FET

During power up with EN/UVLO high and CBST voltage above V(BST_UVLOR) threshold, INP and INP_G controls are active. For the precharge functionality, drive INP low to keep the main FETs OFF and drive INP_G high. G output gets pulled up to BST with IG. Use Equation 5 to calculate the required Cg value.

Equation 5. C g   =   C L O A D   ×   I ( G ) I I N R U S H

Where:

  • I(G) is 100µA (typical)
  • CLOAD is total load capacitance

Use Equation 2 to calculate the IINRUSH. A series resistor Rg must be used in conjunction with Cg to limit the discharge current from Cg during turn-off. The recommended value for Rg is from 220Ω to 470Ω. After the output capacitor is charged, turn OFF the precharge FET by driving INP_G low. G gets pulled low to SRC with an internal 135mA pulldown switch. The main FETs can be turned ON by driving INP high.

Figure 8-8 shows other system design approaches to charge large output capacitors in high current applications. The designs involve an additional power resistor in series in series with precharge FET. The back-to-back FET topology shown is typically used in bi-directional power control applications like battery management systems.

TPS4811-Q1 TPS48111Q1 Application Circuits for Capacitive Load Driving Using Precharge FET and a Series Power Resistor Figure 8-8 TPS48111Q1 Application Circuits for Capacitive Load Driving Using Precharge FET and a Series Power Resistor