SLUSEE5E January   2022  – April 2026 TPS4811-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Recommended Operating Conditions
    3. 6.3 ESD Ratings
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Charge Pump and Gate Driver output (VS, PU, PD, BST, SRC)
      2. 8.3.2 Capacitive Load Driving
        1. 8.3.2.1 FET Gate Slew Rate Control
        2. 8.3.2.2 Using Precharge FET - (with TPS48111Q1 Only)
      3. 8.3.3 Overcurrent and Short-Circuit Protection
        1. 8.3.3.1 Overcurrent Protection With Auto-Retry
        2. 8.3.3.2 Overcurrent Protection With Latch-Off
        3. 8.3.3.3 Short-Circuit Protection
      4. 8.3.4 Analog Current Monitor Output (IMON)
      5. 8.3.5 Overvoltage (OV) and Undervoltage Protection (UVLO)
      6. 8.3.6 Remote Temperature sensing and Protection (DIODE)
      7. 8.3.7 Output Reverse Polarity Protection
      8. 8.3.8 TPS4811x-Q1 as a Simple Gate Driver
    4. 8.4 Device Functional Mode (Shutdown Mode)
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application: Driving HVAC PTC Heater Load on KL40 Line in Power Distribution Unit
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Selection of Current Sense Resistor, RSNS
        2. 9.2.2.2 Selection of Scaling Resistor, RSET
        3. 9.2.2.3 Programming the Overcurrent Protection Threshold - RIWRN Selection
        4. 9.2.2.4 Programming the Short-Circuit Protection Threshold - RISCP Selection
        5. 9.2.2.5 Programming the Fault Timer Period - CTMR Selection
        6. 9.2.2.6 Selection of MOSFET, Q1
        7. 9.2.2.7 Selection of Bootstrap Capacitor, CBST
        8. 9.2.2.8 Setting the Undervoltage Lockout and Overvoltage Set Point
        9. 9.2.2.9 Choosing the Current Monitoring Resistor, RIMON
      3. 9.2.3 Application Curves
    3. 9.3 Typical Application: Driving B2B FETs With Pre-Charging the Output Capacitance
      1. 9.3.1 Design Requirements
      2. 9.3.2 External Component Selection
        1. 9.3.2.1 Selection of Pre-Charge Resistor
      3. 9.3.3 Application Curves
    4. 9.4 Typical Application: Designing for EMI
      1. 9.4.1 Common EMI Components
      2. 9.4.2 Programming the Overcurrent Protection Threshold with Added DC Resistance - RIWRN
      3. 9.4.3 Choosing the Current Monitoring Resistor with Added DC Resistance - RIMON
      4. 9.4.4 Programming the Short Circuit Protection Threshold with Added DC Resistance - RISCP
    5. 9.5 Power Supply and EMI Recommendations
    6. 9.6 Layout
      1. 9.6.1 Layout Guidelines
      2. 9.6.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

9.2.2.4 Programming the Short-Circuit Protection Threshold - RISCP Selection

The RISCP sets the short-circuit protection threshold, whose value can be calculated using Equation 17.

Equation 17. RISCP(Ω)=ISC×RSNS15.6µ - 464

To set 20A as short-circuit protection threshold, RISCP value is calculated to be 1.46kΩ.

Select the closest available standard value: 1.3kΩ, 1%.

In case where large di/dt is involved, the system and layout parasitic inductances can generate large differential signal voltages between ISCP and CS- pins. This action can trigger false short-circuit protection and nuisance trips in the system. To overcome such scenario, TI recommends to add filter capacitor of 1nF across ISCP and CS- pins close to the device. Because nuisance trips are dependent on the system and layout parasitics, TI recommends to test the design in a real system and tweaked as necessary.