SLUSFG2C September   2024  – June 2025 TPS6286A06 , TPS6286A08 , TPS6286A10 , TPS6286B08 , TPS6286B10

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Options
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Rating
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Save Mode (PFM)
      2. 7.3.2 Forced PWM Mode
      3. 7.3.3 Low Dropout Operation (100% Duty Cycle)
      4. 7.3.4 Soft Start
      5. 7.3.5 Switch Current Limit and HICCUP Short-Circuit Protection
      6. 7.3.6 Undervoltage Lockout
      7. 7.3.7 Thermal Warning and Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Enable and Disable (EN)
      2. 7.4.2 Output Discharge
      3. 7.4.3 Power Good (PG)
      4. 7.4.4 Voltage Setting and Mode Selection (VSET/MODE), TPS6286Axx Devices
      5. 7.4.5 Start-Up Output Voltage for TPS6286Bxx Devices
    5. 7.5 Programming
      1. 7.5.1 Serial Interface Description
      2. 7.5.2 Standard-, Fast-, and Fast-Mode Plus Protocol
      3. 7.5.3 HS Mode Protocol
      4. 7.5.4 I2C Update Sequence
      5. 7.5.5 I2C Register Reset
  9. 8 Register Map
    1. 8.1 Target Address Byte
    2. 8.2 Register Address Byte
    3. 8.3 VOUT Register
    4. 8.4 CONTROL Register
    5. 8.5 STATUS Register
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Custom Design With WEBENCH® Tools
        2. 9.2.2.2 Setting the Output Voltage
        3. 9.2.2.3 Output Filter Design
        4. 9.2.2.4 Inductor Selection
        5. 9.2.2.5 Capacitor Selection
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
        1. 9.4.2.1 Thermal Considerations
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Development Support
        1. 10.1.2.1 Custom Design With WEBENCH® Tools
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

7.4.3 Power Good (PG)

The device has an open-drain power-good pin, which is specified to sink up to 1mA. The power-good output requires a pullup resistor connecting to any voltage rail less than 5.5V. The PG has a deglitch delay of 34µs.

The PG signal can be used for sequencing of multiple rails by connecting the PG signal to the EN pin of other converters. Leave the PG pin unconnected when not used.

Table 7-1 PG Function Table
DEVICE CONDITIONSPG PIN
Enable0.9 × VOUT_NOM ≤ VOUT ≤ 1.1 × VOUT_NOMHi-Z
VOUT < 0.9 × VOUT_NOM or VOUT > 1.1 × VOUT_NOMLow
ShutdownEN = lowLow
Thermal shutdownTJ > TJSDLow
UVLO1.8V < VIN < VUVLOLow
Power supply removalVIN < 1.8VUndefined
TPS6286A06 TPS6286A08 TPS6286A10 TPS6286B08 TPS6286B10 Power-Good Transient and Delay BehaviorFigure 7-4 Power-Good Transient and Delay Behavior