SLUSFG2C September   2024  – June 2025 TPS6286A06 , TPS6286A08 , TPS6286A10 , TPS6286B08 , TPS6286B10

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Options
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Rating
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Save Mode (PFM)
      2. 7.3.2 Forced PWM Mode
      3. 7.3.3 Low Dropout Operation (100% Duty Cycle)
      4. 7.3.4 Soft Start
      5. 7.3.5 Switch Current Limit and HICCUP Short-Circuit Protection
      6. 7.3.6 Undervoltage Lockout
      7. 7.3.7 Thermal Warning and Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Enable and Disable (EN)
      2. 7.4.2 Output Discharge
      3. 7.4.3 Power Good (PG)
      4. 7.4.4 Voltage Setting and Mode Selection (VSET/MODE), TPS6286Axx Devices
      5. 7.4.5 Start-Up Output Voltage for TPS6286Bxx Devices
    5. 7.5 Programming
      1. 7.5.1 Serial Interface Description
      2. 7.5.2 Standard-, Fast-, and Fast-Mode Plus Protocol
      3. 7.5.3 HS Mode Protocol
      4. 7.5.4 I2C Update Sequence
      5. 7.5.5 I2C Register Reset
  9. 8 Register Map
    1. 8.1 Target Address Byte
    2. 8.2 Register Address Byte
    3. 8.3 VOUT Register
    4. 8.4 CONTROL Register
    5. 8.5 STATUS Register
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Custom Design With WEBENCH® Tools
        2. 9.2.2.2 Setting the Output Voltage
        3. 9.2.2.3 Output Filter Design
        4. 9.2.2.4 Inductor Selection
        5. 9.2.2.5 Capacitor Selection
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
        1. 9.4.2.1 Thermal Considerations
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Development Support
        1. 10.1.2.1 Custom Design With WEBENCH® Tools
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

6.5 Electrical Characteristics

TJ = –40°C to 125°C, and VIN = 2.4V to 5.5V. Typical values are at TJ = 25°C and VIN = 5V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
IQ_VIN Quiescent current EN = High, no load, device not switching, TJ = 25℃  5.1 9 µA
IQ_OUT Operating quiescent current into OUT pin EN = High, no load, device not switching, VOUT = 1.8V, TJ = 25℃  18 µA
ISD Shutdown current EN = Low, TJ = 25℃
 0.24 0.75 µA
VUVLO Undervoltage lock out threshold VIN rising 2.2 2.3 2.4 V
VIN falling 2.1 2.2 2.3 V
TJSD Thermal shutdown threshold TJ rising 150 °C
Thermal shutdown hysteresis TJ falling 20 °C
TJW Thermal warning threshold TJ rising 130 °C
Thermal warning hysteresis TJ falling 20 °C
LOGIC INTERFACE
VIH High-level input threshold voltage at EN, SCL, SDA and VSET/MODE 0.9 V
VIL Low-level input threshold voltage at EN, SCL, SDA and VSET/MODE 0.4 V
ISCL,LKG Input leakage current into SCL pin TJ = 25℃  0.01 0.2 µA
ISDA,LKG Input leakage current into SDA pin TJ = 25℃  0.01 0.1 µA
IEN,LKG Input leakage current into EN pin TJ = 25℃  0.01 0.1 µA
CSCL Parasictic capacitance at SCL 1 pF
CSDA Parasictic capacitance at SDA 2.4 pF
STARTUP, POWER GOOD
tDelay Enable delay time, TPS6286Axx Time from EN high to device starts switching
249kΩ resistor connected between VSET/MODE and GND		 420 840 1200 µs
tDelay Enable delay time, TPS6286Bxx Time from EN high to device starts switching 100 660 1000 µs
tRamp Output voltage ramp time, TP6286A06 Time from device starts switching to power good (no external capacitor connected) 1 1.5 1.85 ms
tRamp Output voltage ramp time, TP6286A08, TPS6286A10, TPS6286B08, TPS6286B10 Time from device starts switching to power good (no external capacitor connected) 0.4 0.55 0.72 ms
Iss SS pin source current 20 µA
tPG,DLY Power-good deglitch delay Rising and falling edges 34 µs
VPG Power-good lower threshold VOUT referenced to VOUT nominal  85 91 96 %
Power-good upper threshold VOUT referenced to VOUT nominal  103 111 120 %
VPG,OL Low-level output voltage Isink = 1mA 0.36  V
IPG,LKG Input leakage current into PG pin VPG = 5.0V, TJ = 25℃ 0.01 0.1 µA
OUTPUT
VOUT Output voltage accuracy Fixed voltage operation, FPWM, no load, TJ = 25°C –0.7 0.7 %
VOUT Output voltage accuracy Fixed voltage operation, FPWM, no load –1 1 %
VFB Feedback voltage Adjustable voltage operation, TJ = –40°C to 125°C 594 600 606 mV
IFB,LKG Input leakage into FB pin Adjustable voltage operation, VFB = 0.6V, TJ = 25℃ 0.01 0.1  µA
RDIS Output discharge resistor at OUT pin 4.3 Ω
Load regulation VOUT = 0.9V, FPWM  0.04 %/A
POWER SWITCH
RDS(on) High-side FET on-resistance 8 mΩ
Low-side FET on-resistance 8 mΩ
ILIM High-side FET forward current limit TPS6286x06 7.3 8 9 A
ILIM High-side FET forward current limit TPS6286x08 10 11 12 A
ILIM High-side FET forward current limit TPS6286x10 13 14 15 A
ILIM Low-side FET forward current limit TPS6286x06 6.5 A
ILIM Low-side FET forward current limit TPS6286x08 9 A
ILIM Low-side FET forward current limit TPS6286x10 12 A
ILIM Low-side FET negative current limit TPS6286x06, TPS6286x08, TPS6286x10 –3 A
fSW PWM switching frequency IOUT = 1A, VOUT = 0.9V 1.2 MHz