SLUUBT5C November 2018 – June 2021 BQ40Z80
This command returns the SafetyAlert() flags on ManufacturerBlockAccess() or ManufacturerData().
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RSVD | RSVD | OCDL | COVL | UTD | UTC | PCHGC | CHGV | CHGC | OC | CTOS | CTO | PTOS | PTO | RSVD | OTF |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RSVD | CUVC | OTD | OTC | ASC DL | RSVD | ASC CL | RSVD | AOLDL | RSVD | OCD2 | OCD1 | OCC2 | OCC1 | COV | CUV |
| RSVD (Bits 31–30): Reserved. Do not use. | ||
| OCDL (Bit 29): Overcurrent in discharge | ||
| 1 = | Detected | |
| 0 = | Not detected | |
| COVL (Bit 28): Cell overvoltage latch | ||
| 1 = | Detected | |
| 0 = | Not detected | |
| UTD (Bit 27): Undertemperature during discharge | ||
| 1 = | Detected | |
| 0 = | Not detected | |
| UTC (Bit 26): Undertemperature during charge | ||
| 1 = | Detected | |
| 0 = | Not detected | |
| PCHGC (Bit 25): Over-precharge current | ||
| 1 = | Detected | |
| 0 = | Not detected | |
| CHGV (Bit 24): Overcharging voltage | ||
| 1 = | Detected | |
| 0 = | Not detected | |
| CHGC (Bit 23): Overcharging current | ||
| 1 = | Detected | |
| 0 = | Not detected | |
| OC (Bit 22): Overcharge | ||
| 1 = | Detected | |
| 0 = | Not detected | |
| CTOS (Bit 21): Charge timeout suspend | ||
| 1 = | Detected | |
| 0 = | Not detected | |
| CTO (Bit 20): Charge timeout | ||
| 1 = | Detected | |
| 0 = | Not detected | |
| PTOS (Bit 19): Precharge timeout suspend | ||
| 1 = | Detected | |
| 0 = | Not detected | |
| PTO (Bit 18): Precharge timeout | ||
| 1 = | Detected | |
| 0 = | Not detected | |
| RSVD (Bit 17): Reserved. Do not use. | ||
| OTF (Bit 16): Overtemperature FET | ||
| 1 = | Detected | |
| 0 = | Not detected | |
| RSVD (Bit 15): Reserved. Do not use. | ||
| CUVC (Bit 14): Cell undervoltage compensated | ||
| 1 = | Detected | |
| 0 = | Not detected | |
| OTD (Bit 13): Overtemperature during discharge | ||
| 1 = | Detected | |
| 0 = | Not detected | |
| OTC (Bit 12): Overtemperature during charge | ||
| 1 = | Detected | |
| 0 = | Not detected | |
| ASCDL (Bit 11): Short-circuit during discharge latch | ||
| 1 = | Detected | |
| 0 = | Not detected | |
| RSVD (Bit 10): Reserved. Do not use. | ||
| ASCCL (Bit 9): Short-circuit during charge latch | ||
| 1 = | Detected | |
| 0 = | Not detected | |
| RSVD (Bit 8): Reserved. Do not use. | ||
| AOLDL (Bit 7): Overload during discharge latch | ||
| 1 = | Detected | |
| 0 = | Not detected | |
| RSVD (Bit 6): Reserved. Do not use. | ||
| OCD2 (Bit 5): Overcurrent during discharge 2 | ||
| 1 = | Detected | |
| 0 = | Not detected | |
| OCD1 (Bit 4): Overcurrent during discharge 1 | ||
| 1 = | Detected | |
| 0 = | Not detected | |
| OCC2 (Bit 4): Overcurrent during charge 2 | ||
| 1 = | Detected | |
| 0 = | Not detected | |
| OCC1 (Bit 2): Overcurrent during charge 1 | ||
| 1 = | Detected | |
| 0 = | Not detected | |
| COV (Bit 1): Cell overvoltage | ||
| 1 = | Detected | |
| 0 = | Not detected | |
| CUV (Bit 0): Cell undervoltage | ||
| 1 = | Detected | |
| 0 = | Not detected | |