SLUUC72A September   2020  – October 2021 TPS542A50

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Before You Begin
  3. 2Description
    1. 2.1 Typical End-User Applications
    2. 2.2 EVM Features
    3. 2.3 TPS542A50EVM-059 PCB
  4. 3TPS542A50EVM-059 Bottom Circuit
    1. 3.1 Modifications
      1. 3.1.1 Output Voltage Setpoint
      2. 3.1.2 Enable and Undervoltage Lockout
      3. 3.1.3 Programming and External Clock Synchronization
      4. 3.1.4 Load Step with Function Generator
    2. 3.2 TPS542A50EVM-059 Bottom Circuit Schematic
    3. 3.3 Test Setup and Results
      1. 3.3.1  Input/Output Connections
      2. 3.3.2  Start Up Procedure
      3. 3.3.3  Electrical Performance Specifications and Results
      4. 3.3.4  Efficiency
      5. 3.3.5  Power Loss
      6. 3.3.6  Load Regulation
      7. 3.3.7  Transient Response
      8. 3.3.8  Loop Response
      9. 3.3.9  Output Voltage Ripple
      10. 3.3.10 Thermal Data
  5. 4TPS542A50EVM-059 Top Circuit (Small layout area design)
    1. 4.1 Modifications
      1. 4.1.1 Output Voltage Setpoint
      2. 4.1.2 Enable and Undervoltage Lockout
      3. 4.1.3 Programming and External Clock Synchronization
      4. 4.1.4 Load Step with Function Generator
    2. 4.2 TPS542A50EVM-059 Top Circuit (Small Layout Area) Schematic
    3. 4.3 Test Setup and Results
      1. 4.3.1  Input/Output Connections
      2. 4.3.2  Start Up Procedure
      3. 4.3.3  Electrical Performance Specifications and Results
      4. 4.3.4  Efficiency
      5. 4.3.5  Power Loss
      6. 4.3.6  Load Regulation
      7. 4.3.7  Line Regulation
      8. 4.3.8  Transient Response
      9. 4.3.9  Loop Response
      10. 4.3.10 Output Voltage Ripple
      11. 4.3.11 Start Up
  6. 5TPS542A50EVM-059 PCB Layout
  7. 6List of Materials
  8. 7Revision History

4.1.4 Load Step with Function Generator

The TPS542A50EVM-059 has a built-in load that can be controlled using the function generator inputs, FGEN+_2 (TP20_2) and FGEN-_2 (TP21_2). The positive connection of the function generator output is connected to FGEN+_2, and the negative connection of the function generator is connected to FGEN-_2. It is recommended that a 50-Ω termination on the output of the function generator is configured.

The FGEN+_2 input drives the gate of a Texas Instruments CSD17527Q5A N-channel NexFET Power MOSFET. Two 0.02-ohm resistors in parallel (R13_2, R14_2), connected from the source of the CSD17527Q5A to PGND, provide a 0.01-ohm resistance to measure the voltage across to determine output current, which is equal to approximately 10 mV/A. The voltage across these two resistors is measured from J4_2-1 and J4_2-2/3, for the positive and negative terminals, respectively. TI recommends driving the CSD17527Q5A gate with at least 5 V to minimize RDS(on) of the CSD17527Q5A. The safe operating area of the CSD17527Q5A must always be observed when using this feature.