SLUUDG7 December   2025 MSPM33C321A , MSPM33C321A-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Overview of Security Functionality
    1. 1.1 Terminology
  5. 2Secure Execution Environment
    1. 2.1 TrustZone
      1. 2.1.1 Implementation Defined Attribution Unit
      2. 2.1.2 Security Attribution Unit
      3. 2.1.3 TrustZone software development
    2. 2.2 Memory Protection Unit
      1. 2.2.1 TrustZone and MPU
    3. 2.3 Global Security Controller
      1. 2.3.1 GSC Memory configuration
        1. 2.3.1.1 Security Exceptions through the GSC & SAU
        2. 2.3.1.2 Priviledge exceptions with GSC & MPU
  6. 3Security Modules
    1. 3.1 AES
      1. 3.1.1 AES Overview
      2. 3.1.2 AES Usage
        1. 3.1.2.1 Configuration
        2. 3.1.2.2 Setup
        3. 3.1.2.3 Operation
    2. 3.2 Keystore
      1. 3.2.1 Overview
      2. 3.2.2 Keystore Usage
        1. 3.2.2.1 Configuration
        2. 3.2.2.2 Setup
        3. 3.2.2.3 Operation
    3. 3.3 SHA2
      1. 3.3.1 SHA Introduction
        1. 3.3.1.1 SHA features
      2. 3.3.2 SHA Performance
      3. 3.3.3 SHA Usage
        1. 3.3.3.1 Configuration
        2. 3.3.3.2 Setup
        3. 3.3.3.3 Operation
    4. 3.4 PKA
      1. 3.4.1 PKA Introduction
        1. 3.4.1.1 PKA features
      2. 3.4.2 PKA Usage
        1. 3.4.2.1 Configuration
        2. 3.4.2.2 Setup
        3. 3.4.2.3 Operation
    5. 3.5 PQC
      1. 3.5.1 ML-DSA
        1. 3.5.1.1 ML-DSA Introduction
        2. 3.5.1.2 ML-DSA Usage
          1. 3.5.1.2.1 Configuration
          2. 3.5.1.2.2 Setup
          3. 3.5.1.2.3 Operation
  7. 4Revision History

2.2.1 TrustZone and MPU

In the MSPM33C CPUSS the MPU, SAU, and IDAU are used to attribute regions of memory as a combination of different privilege and security levels. This allows the programmer to layer different levels of access by using privilege and security restrictions. An example of the combinations the programmer can use is seen in Figure 2-2. When the device is in Handler mode, the processor is always in a privileged state.

Security and Privileged memory attributes Figure 2-2 Security and Privileged memory attributes