The oscilloscope plots in Figure 3-6 and Figure 3-7 show the start-up behavior of each of these voltage rails while connected to the RTG4 development kit fulfilling the two requirements discussed in Section 2.

As shown in Figure 3-6 and Figure 3-7, both power sequencing requirements have been met and a clean monotonic power-up behavior is observed. Once the voltage rails come up, the RTG4 begins executing its software and the core starts to draw approximately 5-A of current. The software is the SERDES EPCS demo software (DG0624) provided by Microsemi.