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TPS7H3301-SP

ACTIVE

Radiation-hardened QMLV, 2.3-V to 3.5-V input, 3-A sink and source DDR termination LDO regulator

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Data sheet

TPS7H3301-SP

ACTIVE
Data sheet Order now

Product details

DDR memory type DDR2, DDR3, DDR4 Control mode S3, S4/S5 Iout VTT (max) (A) 3 Iq (typ) (mA) 18 Output VREF, VTT Vin (min) (V) 0.9 Vin (max) (V) 3.5 Features Complete Solution, Shutdown Pin for S3 Rating Space Operating temperature range (°C) -55 to 125 Regulator type Linear Regulator Vin bias (max) (V) 3.5 Vin bias (min) (V) 2.375 Vout VTT (min) (V) 0.6
DDR memory type DDR2, DDR3, DDR4 Control mode S3, S4/S5 Iout VTT (max) (A) 3 Iq (typ) (mA) 18 Output VREF, VTT Vin (min) (V) 0.9 Vin (max) (V) 3.5 Features Complete Solution, Shutdown Pin for S3 Rating Space Operating temperature range (°C) -55 to 125 Regulator type Linear Regulator Vin bias (max) (V) 3.5 Vin bias (min) (V) 2.375 Vout VTT (min) (V) 0.6
CFP (HKR) 16 105.6 mm² 11 x 9.6
  • 5962R14228(1):
    • Radiation hardness assurance (RHA) qualified to total ionizing dose (TID) 100 krad(Si)
    • Single event latch-up (SEL), single event gate rupture (SEGR), single event burnout (SEB) immune to LET = 70 MeV-cm2/mg(2)
    • Single event transient (SET), single event functional interrupt (SEFI), and single event upset (SEU) characterized to 70 MeV-cm2/mg(2)
  • Supports DDR, DDR2, DDR3, DDR3L, and DDR4 termination applications
  • Input voltage: supports a 2.5-V and 3.3-V rail(3)
  • Separate low-voltage input (VLDOIN) down to 0.9 V for improved power efficiency(3)
  • 3-A sink and source termination regulator includes droop compensation
  • Enable input and power-good output for power supply sequencing
  • VTT termination regulator
    • Output voltage range: 0.5 to 1.75 V
    • 3-A sink and source current
  • Integrated precision voltage divider network with sense input
  • Remote sensing (VTTSNS)
  • VTTREF buffered reference

    • 49% to 51% accuracy with respect to VDDQSNS (±3 mA)

    • ±10-mA sink and source current
  • Undervoltage lockout (UVLO) and overcurrent limit (OCL) functionality integrated
  • 5962R14228(1):
    • Radiation hardness assurance (RHA) qualified to total ionizing dose (TID) 100 krad(Si)
    • Single event latch-up (SEL), single event gate rupture (SEGR), single event burnout (SEB) immune to LET = 70 MeV-cm2/mg(2)
    • Single event transient (SET), single event functional interrupt (SEFI), and single event upset (SEU) characterized to 70 MeV-cm2/mg(2)
  • Supports DDR, DDR2, DDR3, DDR3L, and DDR4 termination applications
  • Input voltage: supports a 2.5-V and 3.3-V rail(3)
  • Separate low-voltage input (VLDOIN) down to 0.9 V for improved power efficiency(3)
  • 3-A sink and source termination regulator includes droop compensation
  • Enable input and power-good output for power supply sequencing
  • VTT termination regulator
    • Output voltage range: 0.5 to 1.75 V
    • 3-A sink and source current
  • Integrated precision voltage divider network with sense input
  • Remote sensing (VTTSNS)
  • VTTREF buffered reference

    • 49% to 51% accuracy with respect to VDDQSNS (±3 mA)

    • ±10-mA sink and source current
  • Undervoltage lockout (UVLO) and overcurrent limit (OCL) functionality integrated

The TPS7H3301-SP is a TID and SEE radiation-hardened double data rate (DDR) 3-A termination regulator with built-in VTTREF buffer. The regulator is specifically designed to provide a complete, compact, low-noise solution for space DDR termination applications such as single board computers, solid state recorders, and payload processing.

The TPS7H3301-SP supports DDR VTT termination applications using DDR, DDR2, DDR3, DDR4. The fast transient response of the TPS7H3301-SP VTT regulator allows for a very stable supply during read/write conditions. During transients, the fast tracking feature of the VTTREF supply minimizes any voltage offset between VTT/Vo and VTTREF. To enable simple power sequencing, both an enable input and a power-good output (PGOOD) have been integrated into the TPS7H3301-SP. The PGOOD output is open-drain so it can be tied to multiple open-drain outputs to monitor when all supplies have come into regulation. The enable signal can also be used to discharge VTT/Vo during suspend to RAM (S3) power down mode.

The TPS7H3301-SP is a TID and SEE radiation-hardened double data rate (DDR) 3-A termination regulator with built-in VTTREF buffer. The regulator is specifically designed to provide a complete, compact, low-noise solution for space DDR termination applications such as single board computers, solid state recorders, and payload processing.

The TPS7H3301-SP supports DDR VTT termination applications using DDR, DDR2, DDR3, DDR4. The fast transient response of the TPS7H3301-SP VTT regulator allows for a very stable supply during read/write conditions. During transients, the fast tracking feature of the VTTREF supply minimizes any voltage offset between VTT/Vo and VTTREF. To enable simple power sequencing, both an enable input and a power-good output (PGOOD) have been integrated into the TPS7H3301-SP. The PGOOD output is open-drain so it can be tied to multiple open-drain outputs to monitor when all supplies have come into regulation. The enable signal can also be used to discharge VTT/Vo during suspend to RAM (S3) power down mode.
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Technical documentation

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Type Title Date
* Data sheet TPS7H3301-SP Sink and Source Radiation-Hardened 3-A DDR Termination Regulator With Built-In VTTREF Buffer datasheet (Rev. C) PDF | HTML 27 Sep 2024
* Radiation & reliability report TPS7H3301-SP and TPS7H3302-SP Single-Event Effects Radiation Report (Rev. C) 26 Jan 2024
* Radiation & reliability report TPS7H3301-SP Neutron Displacement Damage Characterization 12 Apr 2019
* SMD TPS7H3301-SP SMD 5962-14228 08 Jul 2016
* Radiation & reliability report TPS7H3301-SP Total Ionizing Dose Radiation Report 01 Jul 2016
Application note Hermetic Package Reflow Profiles, Termination Finishes, and Lead Trim and Form (Rev. A) PDF | HTML 05 Nov 2025
Application brief DLA Approved Optimizations for QML Products (Rev. C) PDF | HTML 17 Jun 2025
Application note Heavy Ion Orbital Environment Single-Event Effects Estimations (Rev. B) PDF | HTML 10 Jun 2025
Selection guide TI Space Products (Rev. K) 04 Apr 2025
More literature TI Engineering Evaluation Units vs. MIL-PRF-38535 QML Class V Processing (Rev. B) 20 Feb 2025
Application note Using Space Grade Power Components to Power AMD Kintex XQRKU060 FPGA PDF | HTML 08 Nov 2023
Application note Using Space Grade Power Components to Power Microchip RT PolarFire FPGA PDF | HTML 20 Sep 2023
Application note QML flow, its importance, and obtaining lot information (Rev. C) 30 Aug 2023
Application note Space Grade Power Solution for Microsemi RTG4 PDF | HTML 02 May 2023
Application note TI Space Rated Power Solution for Microsemi® RTG4™ FPGA (Rev. B) PDF | HTML 19 Jan 2023
Application note Single-Event Effects Confidence Interval Calculations (Rev. A) PDF | HTML 19 Oct 2022
Application note DLA Standard Microcircuit Drawings (SMD) and JAN Part Numbers Primer 21 Aug 2020
Application note DDR VTT Power Solutions: A Competitive Analysis (Rev. A) 09 Jul 2020
E-book Radiation Handbook for Electronics (Rev. A) 21 May 2019
Application note External Soft-Start Circuit for TPS7H3301-SP Power-Up Sequencing Applications 07 Jul 2016
Technical article 7 things to know about spacecraft subsystems before your next trip to Mars PDF | HTML 06 Jul 2016

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

TPS7H3301EVM-CVAL — TPS7H3301-SP DDR Termination Evaluation Module

The TPS7H3301-SP source/sink double data rate (DDR) termination regulator is designed to support system needs for low-noise applications.

It is an ntegrated solution with reduced system solution size, improved efficiency and simple system design integration.

User guide: PDF
Not available on TI.com
Development kit

ALPHA-XILINX-KU060-SPACE — Alpha Data® board for Xilinx® Kintex® UltraScale™ XQRKU060 FPGA with TI power

This is a development kit for the Xilinx® XQRKU060 FPGA with industrial -1 speed grade. ADA-SDEV-KIT2 has a modular board design with a XRTC-compatible configuration module, two FMC connectors, DDR3 DRAM, system monitoring, and space-grade TI power management and temperature-sensing solutions.
From: Alpha Data Parallel Systems Ltd.
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Simulation model

TPS7H3301-SP PSpice Transient Model (Rev. B)

SLVMBF1B.ZIP (116 KB) - PSpice Model
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Simulation model

TPS7H3301-SP Unencrypted PSPICE Transient Model

SLVMDD2.ZIP (196 KB) - PSpice Model
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Calculation tool

SLVC650 — TPS7H3301-SP Calculator

Supported products & hardware

Supported products & hardware

Products
DDR memory power ICs
  • TPS7H3301-SP — Radiation-hardened QMLV, 2.3-V to 3.5-V input, 3-A sink and source DDR termination LDO regulator
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CFP (HKR) 16 Ultra Librarian
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