Radiation Hardened 3Amp Sink/Source DDR Termination Regulator w/ Built-in VREF



Product details


DDR memory type DDR, DDR2, DDR3, DDR3L, DDR4, LPDDR2, LPDDR3 Control mode S3, S4/S5 Iout VTT (Max) (A) 3 Iq (Typ) (mA) 18 Output VREF, VTT Vin (Min) (V) 0.9 Vin (Max) (V) 3.5 Features Complete Solution, PGOOD, Shutdown Pin for S3 Rating Space Operating temperature range (C) -55 to 125 open-in-new Find other DDR memory power ICs

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CFP (HKR) 16 - open-in-new Find other DDR memory power ICs


  • 5962R14288(1):
    • Radiation Hardness Assurance (RHA) Qualified to Total Ionizing Dose (TID) 100 krad(Si)
    • Single Event Latch-Up (SEL), Single Event Gate Rupture (SEGR), Single Event Burnout (SEB) Immune to LET = 65 MeV-cm2/mg
    • SET, SEFI, SEU Immune to 65 MeV-cm2/mg
  • Supports DDR, DDR2, DDR3, DDR3LP, and DDR4 Termination Applications and is Compliant to JEDEC Standards
  • Input Voltage: Supports a 2.5-V and 3.3-V Rail(2)
  • Separate Low-Voltage Input (VLDOIN) Down to .9 V for Improved Power Efficiency(2)
  • 3-A Sink and Source Termination Regulator Includes Droop Compensation
  • Enable Input and Power-Good Output for Power Supply Sequencing
  • VTT Termination Regulator
    • Output Voltage Range: 0.5 to 1.75 V
    • 3-A Sink and Source Current
    • ±20-mV Accuracy
  • Integrated Precision Voltage Divider Network With Sense Input
  • Remote Sensing (VOSNS)
  • VTTREF Buffered Reference
    • VDDQ/2 ±1% Accuracy
    • ±10-mA Sink and Source Current
  • Undervoltage Lockout (UVLO), and Overcurrent Limit (OCL) Functionality Integrated

All trademarks are the property of their respective owners.
(1)For all available packages, see the orderable addendum at the end of the data sheet.
(2) Applicable to DDR2, DDR3, DDR3L and DDR4. For DDR, input voltage = 3.3-V nominal. VIN is 2.95 to 3.5 V for DDR1 and VLDOIN > VTT for all DDRs. For DDR2 3-A load condition, VIN is 2.45 to 3.5 V. VIN headroom: VIN_MIN ≥ VTT + 1.5 V.
(3) These units are intended for engineering evaluation only. They are processed to a noncompliant flow (that is, no burn-in, and so forth) and are tested to a temperature rating of 25°C only. These units are not suitable for qualification, production, radiation testing or flight use. Parts are not warranted for performance over the full MIL specified temperature range of –55°C to 125°C or operating life.

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The TPS7H3301-SP is a TID and SEE radiation-hardened double data rate (DDR) 3-A termination regulator with built-in VTTREF buffer. The regulator is specifically design to provide a complete, compact, low-noise solution for space DDR termination applications such as single board computers, solid state recorders, and payload processing.

The TPS7H3301-SP supports and is compliant to DDR, DDR2, DDR3, DDR4, and associated low-power JEDEC specifications. The fast transient response of the TPS7H3301-SP VTT regulator allows for a very stable supply during read/write conditions. During transients, the fast tracking feature of the VTTREF supply minimizes any voltage offset between VTT and VTTREF. To enable simple power sequencing, both an enable input and a power-good output (PGOOD) have been integrated into the TPS7H3301-SP. The PGOOD output is open-drain so it can be tied to multiple open-drain outputs to monitor when all supplies have come into regulation. The enable signal can also be used to discharge VTT during suspend to RAM (S3) power down mode.

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Technical documentation

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Type Title Date
* Datasheet TPS7H3301-SP Sink and Source Radiation-Hardened 3-A DDR Termination Regulator With Built-In VTTREF Buffer datasheet (Rev. A) Jun. 16, 2016
Radiation & Reliability reports Heavy Ion Orbital Environment Single-Event Effects Estimations May 18, 2020
Radiation & Reliability reports Single-Event Effects Confidence Interval Calculations Jan. 14, 2020
More literature Preview: Radiation Handbook for Electronics (Rev. A) Jun. 07, 2019
Solution guides Radiation Handbook for Electronics (Rev. A) May 21, 2019
Selection guides TI Space Products (Rev. G) May 15, 2019
Radiation & Reliability reports TPS7H3301-SP Neutron Displacement Damage Characterization Apr. 12, 2019
Application notes TI Space Rated Power Solution for Microsemi® RTG4™ FPGA (Rev. A) Jul. 27, 2018
Radiation & Reliability reports TPS7H3301-SP Single-Event Effects Radiation Report (Rev. A) Jan. 25, 2017
User guides TPS7H3301EVM-CVAL User's Guide (Rev. A) Oct. 07, 2016
SMD TPS7H3301-SP SMD 5962-14228 Jul. 08, 2016
Application notes External Soft-Start Circuit for TPS7H3301-SP Power-Up Sequencing Applications Jul. 07, 2016
Technical articles 7 things to know about spacecraft subsystems before your next trip to Mars Jul. 06, 2016
Radiation & Reliability reports TPS7H3301-SP Total Ionizing Dose Radiation Report Jul. 01, 2016
Technical articles A New Understanding: Blast Motion redefines movement, tracking and training for athletes. Aug. 06, 2014
Technical articles Improving Fly-Buck Regulation Using Opto (Part-1) Jul. 15, 2014
Technical articles Altium and WEBENCH – together at last Jul. 12, 2014

Design & development

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Hardware development

document-generic User guide

TPS7H3301-SP source/sink Double Data Rate (DDR) termination regulator designed to support system needs for low noise applications.

Integrated solution with reduced system solution size, improved efficiency, and simple system design integration.

  • Source Sink Linear Regulator supporting current up to 3A
  • Low output noise
  • Small size
  • Support DDR, DDR2, DDR3 and DDR4 applications
  • Integrated solution that:
    • Reduces the system solution size
    • Improves efficiency
    • Simplifies design integration
This is a development kit for the Xilinx® XQRKU060 FPGA with industrial -1 speed grade. ADA-SDEV-KIT2 has a modular board design with a XRTC-compatible configuration module, two FMC connectors, DDR3 DRAM, system monitoring, and space-grade TI power management and temperature-sensing solutions.

Design tools & simulation

SLVMBF1B.ZIP (116 KB) - PSpice Model
SLVC650A.ZIP (97 KB)

CAD/CAE symbols

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