SLVAEB1A March   2020  – October 2021 TLV62568 , TLV62569 , TLV62585

 

  1.   Trademarks
  2. 1Introduction
  3. 2Describing the TLV62569 Package Technologies: SOT23-5, SOT23-6, and SOT563
  4. 3Understanding Thermal Performance and Junction Temperature Estimation
    1. 3.1 Understanding Thermal Performance
    2. 3.2 Estimating Junction Temperature
  5. 4Measurement Setup and Test Results
    1. 4.1 Efficiency Measurements
    2. 4.2 Thermal Measurements
  6. 5Thermal Performance Analysis for SOT23-5, SOT23-6, and SOT563 Packages
    1. 5.1 Comparing SOT563 (DRL) and SOT23-6 (DDC)
    2. 5.2 Comparing SOT23-6 (DDC) and SOT23-5 (DBV)
    3. 5.3 Comparing SOT563 (DRL) and SOT23-5 (DBV)
  7. 6Summary
  8. 7References
  9. 8Revision History

2 Describing the TLV62569 Package Technologies: SOT23-5, SOT23-6, and SOT563

The TLV62569 device is a synchronous step-down converter optimized for high efficiency and compact solution size. The device integrates switches capable of delivering an output current up to 2 A. As shown in Table 2-1, this device is available in three different packages: SOT23-5, SOT23-6, and SOT563. In the three packages, the die area remains the same for this device.

Table 2-1 Device Information
PART NUMBER PACKAGE BODY SIZE (NOM)
TLV62569DBV SOT23 (5) 2.90-mm × 2.80-mm
TLV62569PDDC SOT23 (6)
TLV62569DRL SOT563 (6) 1.60-mm × 1.60-mm
TLV62569PDRL SOT563 (6)

As of today, SOT23 packages are widely used in several applications because of their ease of use.

Even though the SOT23-5 (DBV) and SOT23-6 (DDC) share the same package appearance with the same footprint dimensions, these two packages use different interconnection between silicon and package itself. The SOT23-5 (DBV) is designed with a bonding wire interconnection structure whereas the SOT23-6 uses the Flip Chip On Lead (FCOL) approach. Connecting the IC with wire bonds using copper, gold, or aluminum wires inside the package has the advantage of being flexible and cost effective. However, it requires space and the bonding wires add parasitic inductance and resistance on the pins. On the contrary, with the FCOL package technology, copper bumps are used as interconnection and they are directly located on the die. Therefore there is no additional parasitic inductance and resistance added due to the interconnection structure. For more details on SOT23-5 and SOT23-6 packages, see the SOT23 Package Thermal Consideration Application Report.

Similar to the SOT23-6, the new SOT563 (DRL) package is also based on FCOL bonding structure. But SOT563 package interconnection is also different with SOT236 package. Figure 2-1 shows SOT563(DRL) package assembly technology. For SOT236 package, die is under leadframe. As for SOT563 package, die is on leadframe. Obviously lead of SOT563 is shorter. Short lead will lead to small parasitic resister and inductance. Thanks to innovations in packaging structures and lead frame designs, it is possible to achieve a 65% smaller IC package compared to SOT23-5 and SOT23-6 for the same die area without compromising thermal performance. Table 3-3 shows that the junction to top and junction to board thermal characteristics ψJT and ψJB are the smallest for the DRL package, translating directly in a better heat dissipation of the junction to top and junction to board. Table 3-4 shows TPS563201 and TPS563202 part thermal metric. ψJT of TPS563202 is smaller than TPS563201 which also shows DRL package has a better heat dissipation of the junciton to top.

Figure 2-1 SOT563 package