SLVAF93A october   2022  – april 2023 LP8764-Q1 , TPS6594-Q1

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
  4. 2Hardware and PMIC Setup
  5. 3Configuration Overview
  6. 4Instructions
  7. 5Special Considerations
    1. 5.1 Changing the Serial Control Interface
    2. 5.2 Updating the Frequency Selection
    3. 5.3 PFSM
    4. 5.4 Permanently Locking the NVM
    5. 5.5 Updating the Register CRC
  8. 6NVM Validation
  9. 7References
  10.   A Registers Backed by NVM
  11.   B Non-NVM Registers Which are Part of the Register CRC
  12.   C CRC for User Registers, Page 0 and Page 4
  13.   D Example With I2C Serial Interface
  14.   E Revision History

6 NVM Validation

After the NVM has been updated and the PMIC power cycled, the NVM contents can be validated by simply reading out the user register map. Consideration is required if the PFSM instructions overwrite register settings during power up.

Alternatively, the NVM can be unlocked, the PFSM halted, and the NVM content directly transferred to the user registers. Once the NVM content is transferred to the user registers the values are again accessible through the serial interface. This alternative method is described in Table 6-1.

Note: If the NVM is locked, then the alternative mode described in Table 6-1 is not possible. Only user registers, Page 0 and Page 4, can be verified.

Table 6-1 NVM Validation Example
Instruction I2C Address (Page) Read/ Write Register Address Data Description
1 0x28 (0) Write 0xA2 0x00 Reset unlock logic
2 0x28 (0) Write 0xA2 0x98 NVM Unlock Sequence
3 0x28 (0) Write 0xA2 0xB8
4 0x28 (0) Write 0xA2 0x13
5 0x28 (0) Write 0xA2 0x7D
6 0x28 (0) Read 0xA3 0xC0 Confirm that the NVM was successfully unlocked; bit 6 is set
7 0x28 (0) Write 0xA3 0xC1 Halt the PFSM
8 0x29 (1) Write 0xEF 0x01 Transfer configuration from NVM to user registers
9 0x29 (1) Read 0xF3 0x04 Confirm that the transfer is complete; bit 1 is cleared. Bit 2 is a don't care.
10 0x29 (1) Read 0x23 0x12 Determine the I2C2 address to read from
11 0x28 (0) Read 0x01-0xFF Array Read content from page 0. See Appendix A for valid address ranges.
12 0x29 (1) Read 0x00-0xFF Array Read content from page 1. See Appendix A for valid address ranges.
13 0x12 (4) Read 0x00-0x0A Array Read content from page 4. See Appendix A for valid address ranges.
14 0x28 (0) Write 0xA4 0x00 Set PFSM to sub-page 0
15 0x2B (3) Read 0x00-0xFF Array Read content from page 3, sub-page 0
16 0x28 (0) Write 0xA4 0x01 Set PFSM to sub-page 1
17 0x2B (3) Read 0x00-0xFF Array Read content from page 3, sub-page 1
18 0x28 (0) Write 0xA4 0x02 Set PFSM to sub-page 2
19 0x2B (3) Read 0x00-0xFF Array Read content from page 3, sub-page 2
20 0x28 (0) Write 0xA4 0x00 Set PFSM to sub-page 0
21 0x28 (0) Write 0xA2 0x00 Reset unlock logic