SLVAF93A october   2022  – april 2023 LP8764-Q1 , TPS6594-Q1

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
  4. 2Hardware and PMIC Setup
  5. 3Configuration Overview
  6. 4Instructions
  7. 5Special Considerations
    1. 5.1 Changing the Serial Control Interface
    2. 5.2 Updating the Frequency Selection
    3. 5.3 PFSM
    4. 5.4 Permanently Locking the NVM
    5. 5.5 Updating the Register CRC
  8. 6NVM Validation
  9. 7References
  10.   A Registers Backed by NVM
  11.   B Non-NVM Registers Which are Part of the Register CRC
  12.   C CRC for User Registers, Page 0 and Page 4
  13.   D Example With I2C Serial Interface
  14.   E Revision History

C CRC for User Registers, Page 0 and Page 4

Table 10-1 includes the data or data references and the appropriate masks as described in Section 5.5.

Table C-1 Data and Masks for User Registers CRC calculation
Address TP659x-Q1 Data LP876x-Q1 Data TPS659x-Q1 Include Mask TPS659x-Q1 Exclude Mask LP876x-Q1 Include Mask LP876x-Q1 Exclude Mask
0x00 0x00 0x00 NA3 NA3 NA3 NA3
0x011 Read from Device Read from Device 0xFF 0xFF 0xFF 0xFF
0x021 Read from Device Read from Device 0xFF 0xFF 0xFF 0xFF
0x031 Read from Device Read from Device 0xFF 0xFF 0xFF 0xFF
0x04 NVM2 NVM 0xFF 0xBF 0xFF 0xBF
0x05 NVM NVM 0xFF 0x3F 0xFF 0x3F
0x06 NVM NVM 0xFF 0xBB 0xFF 0xBB
0x07 NVM NVM 0xFF 0x3F 0xFF 0x3F
0x08 NVM NVM 0xFF 0xBF 0xFF 0xBF
0x09 NVM NVM 0xFF 0x3F 0xFF 0x3F
0x0A NVM NVM 0xFF 0xBB 0xFF 0xBB
0x0B NVM NVM 0xFF 0x3F 0xFF 0x3F
0x0C NVM 0x00 0xFF 0xBB NA NA
0x0D NVM 0x00 0xFF 0x3F NA NA
0x0E NVM NVM 0xFF 0xFF 0xFF 0xFF
0x0F NVM NVM 0xFF 0xFF 0xFF 0xFF
0x10 NVM NVM 0xFF 0xFF 0xFF 0xFF
0x11 NVM NVM 0xFF 0xFF 0xFF 0xFF
0x12 NVM NVM 0xFF 0xFF 0xFF 0xFF
0x13 NVM NVM 0xFF 0xFF 0xFF 0xFF
0x14 NVM NVM 0xFF 0xFF 0xFF 0xFF
0x15 NVM NVM 0xFF 0xFF 0xFF 0xFF
0x16 NVM 0x00 0xFF 0xFF NA NA
0x17 NVM 0x00 0xFF 0xFF NA NA
0x18 NVM NVM 0xFF 0x3F 0xFF 0x3F
0x19 NVM NVM 0xFF 0x3F 0xFF 0x3F
0x1A NVM NVM 0xFF 0x3F 0xFF 0x3F
0x1B NVM NVM 0xFF 0x3F 0xFF 0x3F
0x1C NVM 0x00 0xFF 0x3F NA NA
0x1D NVM 0x00 0xFF 0xF3 NA NA
0x1E NVM 0x00 0xFF 0xF3 NA NA
0x1F NVM 0x00 0xFF 0xF3 NA NA
0x20 NVM 0x00 0xFF 0xF3 NA NA
0x21 0x00 0x00 0x00 0x00 0x00 0x00
0x22 0x00 0x00 0xFF 0x01 NA NA
0x23 NVM 0x00 0xFF 0xFE NA NA
0x24 NVM 0x00 0xFF 0xFE NA NA
0x25 NVM 0x00 0xFF 0xFE NA NA
0x26 NVM 0x00 0xFF 0x7F NA NA
0x27 NVM 0x00 0xFF 0x3F NA NA
0x28 NVM 0x00 0xFF 0x3F NA NA
0x29 NVM 0x00 0xFF 0x3F NA NA
0x2A NVM 0x00 0xFF 0x3F NA NA
0x2B NVM NVM 0xFF 0x21 0xFF 0xFF
0x2C NVM NVM 0xFF 0x7F 0xFF 0x7F
0x2D 0x00 NVM NA(3) NA(3) 0xFF 0x7F
0x2E 0x00 NVM NA NA 0xFF 0xFF
0x2F 0x00 NVM NA NA 0xFF 0x7F
0x30 0x00 NVM NA NA 0xFF 0xFF
0x31 NVM NVM 0xFF 0xFF 0xFF 0xFF
0x32 NVM NVM 0xFF 0xFF 0xFF 0xFF
0x33 NVM NVM 0xFF 0x10 0xFF 0xFF
0x34 NVM NVM 0xFF 0x10 0xFF 0xFF
0x35 NVM NVM 0xFF 0xFF 0xFF 0xFF
0x36 NVM NVM 0xFF 0xFF 0xFF 0xFF
0x37 NVM NVM 0xFF 0xFF 0xFF 0xFF
0x38 NVM NVM 0xFF 0xFF 0xFF 0xFF
0x39 NVM NVM 0xFF 0xFF 0xFF 0xFF
0x3A NVM NVM 0xFF 0xFF 0xFF 0xFF
0x3B NVM 0x00 0xFF 0xFF NA NA
0x3C NVM NVM 0xFF 0x11 0xFF 0x00
0x3D NVM NVM 0xFF 0xFF 0xFF 0xFF
0x3E NVM NVM 0xFF 0x07 0xFF 0x03
0x3F 0x00 0x00 NA NA NA NA
0x40 0x00 0x00 NA NA NA NA
0x41 NVM NVM 0xFF 0xFF 0xFF 0xFF
0x42 NVM 0x00 0xFF 0xFF NA NA
0x43 NVM NVM 0xFF 0x0F 0xFF 0xFC
0x44 NVM NVM 0xFF 0xFF 0xFF 0xFF
0x45 NVM NVM 0xFF 0x03 0xFF 0x03
0x46 NVM NVM 0xFF 0xFF 0xFF 0xFF
0x47 NVM NVM 0xFF 0xFF 0xFF 0xFF
0x48 NVM NVM 0xFF 0x3F 0xFF 0x0F
0x49 NVM NVM 0xFF 0xBB 0xFF 0xBB
0x4A NVM NVM 0xFF 0xBB 0xFF 0xBB
0x4B NVM 0x00 0xFF 0x0B NA NA
0x4C NVM 0x00 0xFF 0xBB NA NA
0x4D NVM 0x00 0xFF 0xBB NA NA
0x4E NVM NVM 0xFF 0x03 0xFF 0x6F
0x4F NVM NVM 0xFF 0xF3 0xFF 0xFF
0x50 NVM NVM 0xFF 0xF3 0xFF 0xFF
0x51 NVM NVM 0xFF 0x3F 0xFF 0x1B
0x52 NVM NVM 0xFF 0x20 0xFF 0x00
0x53 NVM NVM 0xFF 0x0B 0xFF 0x0B
0x54 NVM NVM 0xFF 0xD6 0xFF 0xD6
0x55 0x00 0x00 NA NA NA NA
0x56 NVM NVM 0xFF 0x0F 0xFF 0x8F
0x57 NVM NVM 0xFF 0xAB 0xFF 0xAB
0x58 NVM NVM 0xFF 0x09 0xFF 0x09
0x59 NVM NVM 0xFF 0x3F 0xFF 0x38
0x5A 0x00 0x00 NA NA NA NA
0x5B 0x00 0x00 NA NA NA NA
0x5C 0x00 0x00 NA NA NA NA
0x5D 0x00 0x00 NA NA NA NA
0x5E 0x00 0x00 NA NA NA NA
0x5F 0x00 0x00 NA NA NA NA
0x60 0x00 0x00 NA NA NA NA
0x61 0x00 0x00 NA NA NA NA
0x62 0x00 0x00 NA NA NA NA
0x63 0x00 0x00 NA NA NA NA
0x64 0x00 0x00 NA NA NA NA
0x65 0x00 0x00 NA NA NA NA
0x66 0x00 0x00 NA NA NA NA
0x67 0x00 0x00 NA NA NA NA
0x68 0x00 0x00 NA NA NA NA
0x69 0x00 0x00 NA NA NA NA
0x6A 0x00 0x00 NA NA NA NA
0x6B 0x00 0x00 NA NA NA NA
0x6C 0x00 0x00 NA NA NA NA
0x6D 0x00 0x00 NA NA NA NA
0x6E 0x00 0x00 NA NA NA NA
0x6F 0x00 0x00 NA NA NA NA
0x70 0x00 0x00 NA NA NA NA
0x71 0x00 0x00 NA NA NA NA
0x72 0x00 0x00 NA NA NA NA
0x73 0x00 0x00 NA NA NA NA
0x74 0x00 0x00 NA NA NA NA
0x75 0x00 0x00 NA NA NA NA
0x76 0x00 0x00 NA NA NA NA
0x77 0x00 0x00 NA NA NA NA
0x78 NVM NVM 0xFF 0xFF 0xFF 0xFF
0x79 NVM 0x00 0xFF 0x03 NA NA
0x7A NVM 0x00 0xFF 0xFF NA NA
0x7B NVM NVM 0xFF 0xF9 0xFF 0xFF
0x7C NVM NVM 0xFF 0x03 0xFF 0x03
0x7D NVM NVM 0xFF 0xFB 0xFF 0xFB
0x7E NVM 0x00 0x7F 0x0F NA NA
0x7F 0x00 0x00 NA NA NA NA
0x80 0x00 0x00 0xFF 0x01 0xFF 0x01
0x81 0x00 0x00 0xFF 0xFF 0xFF 0xFF
0x82 0x08 0x08 0xF8 0x18 0xF8 0x18
0x83 0x00 0x00 NA NA NA NA
0x84 NVM NVM 0xEF 0x0F 0xEF 0x0F
0x85 0x00 0x00 0xF0 0xF0 0xF0 0xF0
0x86 0x00 0x00 0xFF 0x03 0xFF 0x03
0x87 NVM NVM 0xFF 0x1F 0xFF 0x0F
0x88 NVM NVM 0xFF 0x07 0xFF 0x07
0x89 0x00 0x00 NA NA NA NA
0x8A NVM NVM 0xFF 0x1F 0xFF 0xFF
0x8B NVM NVM 0xFF 0x1F 0xFF 0x1F
0x8C NVM 0x00 0xFF 0xFF NA NA
0x8D NVM 0x00 0xFF 0xFF NA NA
0x8E NVM NVM 0xFF 0x0F 0xFF 0x0F
0x8F 0x00 0x00 0xFF 0x01 0xFF 0x01
0x90 0x00 0x00 0xFF 0xFF 0xFF 0xFF
0x91 0x00 0x00 0xFF 0xFF 0xFF 0xFF
0x92(4) 0x00 0x00 0xFF 0xEF 0xFF 0xEF
0x93 0x00 0x00 0xFF 0xFF 0xFF 0xFF
0x94 0x00 0x00 0xFF 0xFF 0xFF 0xFF
0x95 0x00 0x00 0xFF 0xFF 0xFF 0xFF
0x96 0x00 0x00 0xFF 0xFF 0xFF 0xFF
0x97 0x00 0x00 NA NA NA NA
0x98 0x00 0x00 0xFF 0x01 NA NA
0x99 0x00 0x00 0xFF 0xFF NA NA
0x9A 0x00 0x00 0xFF 0xFF NA NA
0x9B(4) 0x00 0x00 0xFF 0xEF NA NA
0x9C 0x00 0x00 0xFF 0xFF NA NA
0x9D 0x00 0x00 0xFF 0xFF NA NA
0x9E 0x00 0x00 0xFF 0xFF NA NA
0x9F 0x00 0x00 0xFF 0xFF NA NA
0xA0 0x00 0x00 NA NA NA NA
0xA1 0x00 0x00 NA NA NA NA
0xA2 0x00 0x00 NA NA NA NA
0xA3 0x00 0x00 NA NA NA NA
0xA4 0x00 0x00 NA NA NA NA
0xA5 0x00 0x00 NA NA NA NA
0xA6 0x00 0x00 NA NA NA NA
0xA7 NVM NVM 0xFF 0xFF 0xFF 0xFF
0xA8 0x00 NVM NA NA 0xFF 0x3F
0xA9 0x00 0x00 NA NA NA NA
0xAA 0x00 0x00 NA NA NA NA
0xAB 0x00 0x00 NA NA NA NA
0xAC 0x00 0x00 NA NA NA NA
0xAD 0x00 0x00 NA NA NA NA
0xAE 0x00 0x00 NA NA NA NA
0xAF 0x00 0x00 NA NA NA NA
0xB0 0x00 0x00 NA NA NA NA
0xB1 0x00 0x00 NA NA NA NA
0xB2 0x00 0x00 NA NA NA NA
0xB3 0x00 0x00 NA NA NA NA
0xB4 0x00 0x00 NA NA NA NA
0xB5 0x00 0x00 NA NA NA NA
0xB6 0x00 0x00 NA NA NA NA
0xB7 0x00 0x00 NA NA NA NA
0xB8 0x00 0x00 NA NA NA NA
0xB9 0x00 0x00 NA NA NA NA
0xBA 0x00 0x00 NA NA NA NA
0xBB 0x00 0x00 NA NA NA NA
0xBC 0x00 0x00 NA NA NA NA
0xBD 0x00 0x00 NA NA NA NA
0xBE 0x00 0x00 NA NA NA NA
0xBF 0x00 0x00 NA NA NA NA
0xC0 0x00 0x00 NA NA NA NA
0xC1 0x00 0x00 NA NA NA NA
0xC2 0x00 0x00 NA NA NA NA
0xC3(4) NVM NVM 0xFF 0x00 0xFF 0x00
0xC4 0x00 0x00 NA NA NA NA
0xC5 0x00 0x00 NA NA NA NA
0xC6 0x00 0x00 NA NA NA NA
0xC7 0x00 0x00 NA NA NA NA
0xC8 0x00 0x00 NA NA NA NA
0xC9 0x00 0x00 0xFF 0x00 0xFF 0x00
0xCA 0x00 0x00 0xFF 0x00 0xFF 0x00
0xCB 0x00 0x00 0xFF 0x00 0xFF 0x00
0xCC 0x00 0x00 0xFF 0x00 0xFF 0x00
0xCD NVM NVM 0xFF 0x00 0xFF 0x00
0xCE NVM NVM 0xFF 0x00 0xFF 0x00
0xCF NVM NVM 0xFF 0x00 0xFF 0x00
0xD0 NVM NVM 0xFF 0x00 0xFF 0x00
0xD1 NVM 0x00 0xFF 0x00 NA NA
0xD2 0x00 0x00 NA NA NA NA
0xD3 0x00 0x00 NA NA NA NA
0xD4 0x00 0x00 NA NA NA NA
0xD5 0x00 0x00 NA NA NA NA
0xD6 0x00 0x00 NA NA NA NA
0xD7 0x00 0x00 NA NA NA NA
0xD8 0x00 0x00 NA NA NA NA
0xD9 0x00 0x00 NA NA NA NA
0xDA 0x00 0x00 NA NA NA NA
0xDB 0x00 0x00 NA NA NA NA
0xDC 0x00 0x00 NA NA NA NA
0xDD 0x00 0x00 NA NA NA NA
0xDE 0x00 0x00 NA NA NA NA
0xDF 0x00 0x00 NA NA NA NA
0xE0 0x00 0x00 NA NA NA NA
0xE1 0x00 0x00 NA NA NA NA
0xE2 0x00 0x00 NA NA NA NA
0xE3 0x00 0x00 NA NA NA NA
0xE4 0x00 0x00 NA NA NA NA
0xE5 0x00 0x00 NA NA NA NA
0xE6 0x00 0x00 NA NA NA NA
0xE7 0x00 0x00 NA NA NA NA
0xE8 0x00 0x00 NA NA NA NA
0xE9 0x00 0x00 NA NA NA NA
0xEA 0x00 0x00 NA NA NA NA
0xEB 0x00 0x00 NA NA NA NA
0xEC 0x00 0x00 NA NA NA NA
0xED 0x00 0x00 NA NA NA NA
0xEE 0x00 0x00 NA NA NA NA
0xEF 0x00 0x00 NA NA NA NA
0xF0 0x00 0x00 0xFF 0xFF 0xFF 0xFF
0xF1 0x00 0x00 NA NA NA NA
0xF2 0x7F 0x7F 0xFF 0x7F 0xFF 0x7F
0xF3 0x7F 0x7F 0xFF 0x7F 0xFF 0x7F
0xF4 Page 4, Register 0x05(5) NVM Page 4, Register 0x05(5) 0xFF 0xFF 0xFF 0xFF
0xF5 0x00 0x00 NA NA NA NA
0xF6 0x0A 0x0A 0xFF 0xFF 0xFF 0xFF
0xF7 0x00 0x00 NA NA NA NA
0xF8 Page 4, Register 0x09(6) NVM Page 4, Register 0x09(6) 0xFF 0xFF 0xFF 0xFF
0xF9 0x00 0x00 NA NA NA NA
0xFA 0x00 0x00 NA NA NA NA
0xFB 0x00 0x00 NA NA NA NA
0xFC 0x00 0x00 NA NA NA NA
0xFD 0x00 0x00 NA NA NA NA
0xFE 0x00 0x00 NA NA NA NA
0xFF 0x00 0x00 NA NA NA NA
(1) Register addresses 0x01, 0x02, and 0x03 of Page 0 (DEV_REV, NVM_CODE_1, and NVM_CODE_2) are programmed in the factory and cannot be changed. These values are part of the register CRC calculation and must be read from the device.
(2) NVM means that this register is backed by NVM and the value is be read from the .BIN file generated from the GUI (see Reference 3).
(3) NA means that the CRC mask is not applicable. In the algorithm the value used to update the CRC is the logical 'AND' of the data and the mask. If either the data or the mask is '0x00' then the result is 0x00. From the algorithm this can be interpreted as an undefined register.
(4) Register addresses 0x92, 0x9B, and 0xC3 are a mix of bits which are backed by NVM and bits which are not backed by NVM. The NVM backed bits, ESM_MCU_EN and ESM_SOC_EN, found in registers 0x92 and 0x9B, respectively, are typically '0'. Enabling the ESM immediately upon power up is not recommended. FIRST_STARTUP_DONE, found in register 0xC3 is not backed by NVM and is '0' by default.
(5) Page 4, Register 0x05 is the WD_LONGWIN register. This value is taken from address 0x405 found in the GUI generated .BIN file.
(6) Page 4, Register 0x09 is the WD_THR_CFG register. This value is taken from address 0x405 found in the GUI generated .BIN file. Only bit 6, WD_EN, is backed by NVM but the other bits are set by default. Therefore this value is either 0xFF or 0xBF.