SLVAF93A october   2022  – april 2023 LP8764-Q1 , TPS6594-Q1

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
  4. 2Hardware and PMIC Setup
  5. 3Configuration Overview
  6. 4Instructions
  7. 5Special Considerations
    1. 5.1 Changing the Serial Control Interface
    2. 5.2 Updating the Frequency Selection
    3. 5.3 PFSM
    4. 5.4 Permanently Locking the NVM
    5. 5.5 Updating the Register CRC
  8. 6NVM Validation
  9. 7References
  10.   A Registers Backed by NVM
  11.   B Non-NVM Registers Which are Part of the Register CRC
  12.   C CRC for User Registers, Page 0 and Page 4
  13.   D Example With I2C Serial Interface
  14.   E Revision History

5.1 Changing the Serial Control Interface

The serial control interface registers are 0x11A, 0x122, and 0x123. As shown in Table 5-1, 0x11A is the serial interface register and indicates if the serial interface is either I2C or SPI and if the CRC is enabled on the interfaces, I2C1 or SPI and I2C2. The I2C1 address is stored in 0x122 and the I2C2 address is stored in 0x123.

Table 5-1 Serial Interface Register
Page 1, Register Address 0x1A Bit Field Description
Bit 2
  • 0 = I2C2 CRC Disabled
  • 1 = I2C2 CRC Enabled
Bit 1
  • 0 = I2C1 or SPI CRC Disabled
  • 1 = I2C1 or SPI CRC Enabled
Bit 0
  • 0 = I2C Mode
  • 1 = SPI Mode

Once the NVM is successfully unlocked, the serial interface can be changed. Once the change is made, the previous serial interface no longer applies and the interface must change appropriately on the host side. In the context of an I2C address change, the necessary updates must be made for the pages. For example, if the I2C1 address is changed from 0x48 to 0x28, then pages before and after the change are represented in Table 5-2.

Table 5-2 I2C Address and Page Relationship
Page1
  • I2C1 Address = 0x48
  • I2C2 Address = 0x12
  • I2C1 Address = 0x28
  • I2C2 Address = 0x12
Page 0 0x48 0x28
Page 1 0x49 0x29
Page 3 0x4B 0x2B
Page 4 0x12 0x12
(1) Page 4 is always directly associated with I2C2 and page 0 is directly associated with I2C1. Pages 1 and 3 are always offset from page 0.

For a change from SPI to I2C or I2C to SPI, the necessary GPIO must be available to support both interfaces. Provide a wait or delay so that the hardware is correctly configured to the desired serial interface before proceeding with the NVM instructions. See the device data sheet for an explanation of the I2C interface and SPI.

Note:

While the NVM is unlocked, the I2C2 physical interface is not used and all pages are accessed from I2C1 of the PMIC(SDA_I2C1, SCL_I2C1).