4 Instructions

These instructions refer to pages and register addresses. When an I²C serial interface is used, the pages are delineated by distinct I²C addresses while in SPI the page information is included in the second byte of the transmission payload. The serial interface can be changed as part of the NVM configuration as discussed in Section 5. See the device data sheet regarding page implementation.

1. Unlocking the NVM
   Unlocking the NVM requires a series of write accesses to the USER_EE_CTRL_1 register located at register address 0xA2 in page 0. Write ‘0x00’ to the register first to reset the unlock mechanism. The next four writes must occur in order and no register accesses can be performed in between the writes. First, 0x98, second, 0xB8, third, 0x13, and fourth 0x7D. When the NVM has been successfully unlocked, both bits 6 and 7 of register address 0xA3 in page 0 are set.
   Note: Register accesses include the PFSM as well as the serial interface. During the unlocking of the NVM, the PMIC must be in an idle state and the PFSM is not attempting to access the register map. The MCU performing the unlock must also limit register accesses to only those writes associated with the unlock sequence. In some MCU serial communications an automatic readback of each register is performed after each write. Any such mechanism must be turned off.
2. Disable the PFSM
   Once the NVM has been unlocked the next step is to disable the PFSM. This is done by setting bit 0 of register address 0xA3 in page 0. Since this register also contains the contents of the unlock, write 0xC1 to the register.
3. Special Considerations for Buck Frequency and Serial Interface Changes
   After disabling the PFSM and before writing the new content to the user registers any special considerations for buck frequency or interface changes must be applied. If the buck frequency remains the same and the serial interface is unchanged then no additional instructions are required. See the applicable special considerations as well as the example. Details are provided in Section 5.1 and Section 5.2
4. Writing Content to pages 0, 1, and 4
   Writing to pages 0, 1, and 4 must only include the register addresses described in Appendix A. In the event that the register CRC is enabled, then non-NVM registers must also be returned to their default value as described in Appendix B.
5. Writing Content to page 3
   After completion of pages 0,1, and 4, write to page 3. Page 3 is a special use case and requires additional handling to access the sub-pages for the PFSM memory space. The page and sub-page delineations can also be identified in the binary file, where page 0 is in the address space 0x00-0xFF, page 1 is 0x100-0x1FF, page 4 is 0x400-0x4FF, and page 3, sub-page 0, is 0x3000-0x30FF, sub-page 1 is 0x3100-0x31FF, and sub-page 2 is 0x3200-0x32FF. A detailed description of the sub-pages is found in the PFSM section. Selecting the Page 3 sub-pages is done through register 0xA4 on Page 0.
   CAUTION: The TPS6594-Q1 and TPS6593-Q1 family of devices have three subpages for page 3. The LP8764-Q1 device only has two subpages for page 3 and sub-page 2 does not exist. Attempting to write to sub-page 2 of the LP8764-Q1 results in writing to sub-page 1, corrupting the memory space.
   Table 4-1 PFSM Address Control, Register Address 0xA4, Page 0

   Bit	Field	Type	Reset	Description
   7-2	Reserved	R/W	0h
   1-0	PFSM_PAGE_SEL	R/W	0h	Select the Page 3 address space that can be addressed. 0: 0x000-0x0FF 1: 0x100-0x1FF 2: 0x200-0x2FF

6. Lock the NVM to prevent future programming (optional)
   If locking the NVM to prevent future updates is desired, then the value of register 0x41 on page 1 must be something other than 0xA5. Locking the NVM also prevents the ability to access page 3 for validation purposes.
   Note: Locking the NVM is a permanent decision and prohibits any future changes.
7. Update register CRC
   After all of the content has been updated in the register map, then the register CRC can be calculated and applied. This is only necessary if the register CRC is enabled in the NVM being configured.
8. Move content from register map to NVM
   Now that all of the user register content has been updated and the register CRC updated, the contents can be copied into the NVM space. To initiate the transfer of content, set bit 1 of register 0xEF in page 1. The transfer is not instantaneous and the status of the transfer can be observed in bit 1 of register address 0xF3 in page 1. When this bit is cleared then the transfer activity is complete.