1 Introduction

A typical power tree of an enterprise server motherboard is shown in Figure 1-1. With the advancement of artificial intelligence and machine learning, graphics processing units (GPUs) are becoming more and more power-hungry over time and demand high slew-rate and amplitude current pulses to improve the processor computation speed. Figure 1-2 depicts a typical load transient profile seen at the 12V bus (50A to 110A load transient) while applying a load transient of 300A for 8ms to 675A for 2ms and then 300A for 8ms (as per Intel® Birch Stream server platform) at the output of VRM with 1.8V. To support these load transients at the output of the voltage regulator modules (VRMs), the power stages of the VRMs have to draw the pulse currents from the input power supply unit (PSU) as the input and output filters of the VRMs are unable to support these high-frequency load transients. As shown in Figure 1-1, the input power path protection devices, eFuses are placed in between the PSU and the power stages of VRMs for inrush current management and protecting the PSUs and the VRMs against different faults, such as input under-voltage, input over-voltage, power up into output short, over-current, output hot-short, etc. The over-current protection mechanism needs to be implemented inside the eFuses so that these devices can protect the system against a persistent over-current fault whereas the transient peak current pulses of a certain amplitude and duration must be allowed to pass through.

Figure 1-1 Enterprise Server Power Block Diagram

Figure 1-2 A Typical Load Transient Profile Seen at the 12V Bus Powering a VRM with 1.8V Output