SLVAFW3B March   2025  – October 2025 AM62L , TPS65214

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Power Management IC (PMIC) Overview
  6. 3Low Power Modes and Power Supply Optimization
    1. 3.1 PDN#1: Optimized Power Design for BOM Size and Cost
    2. 3.2 PDN#2: Optimized Power Design for Lowest Suspend Power
    3. 3.3 PDN#3: Fully Flexible Power Design
    4. 3.4 PDN#4: Power Supply Implementation for DDR4
  7. 4Power-Up Sequence
  8. 5Power-Down Sequence
  9. 6Summary
  10. 7References
  11.   A Appendix A: Discrete Power Implementation for PDN#1
  12.   B Revision History

3.1 PDN#1: Optimized Power Design for BOM Size and Cost

The Power Delivery Network (PDN) described in this section offers a power design optimized for smaller BOM size and lower cost. The design uses a single 3.5mm × 3.5mm Power Management IC (PMIC) to supply all the SoC power domains. Alternatively, discrete components can be used to implement the power design. Figure 3-1 shows the PMIC implementation. This PDNs can be used for applications not using RTC only and RTC + IO + DDR low power modes.

Highlights:

  • Estimated BOM size: 36.97mm2 (does not include PCB clearance).
  • All SoC voltage domains are supplied with a single PMIC if total current on 3.3V IO (including AM62L + peripherals) is lower than 500mA.
  • If total current on 3.3V IO (including AM62L + peripherals) is higher than 500mA, refer to Section 3.2
  • When using 3.3V input supply (lowest power consumption), PMIC LDO2 is configured as 3.3V load-switch.
  • When using 4V-5V input supply, PMIC LDO2 is configured as 3.3V LDO.
AM62L PDN Optimized for BOM Size and Cost Figure 3-1 AM62L PDN Optimized for BOM Size and Cost
Note: The power-switch connected to VDDA_3P3_SDIO is optional and only needed if the application uses SD card. The VPP 1.8V LDO is optional and only needed if on-board eFuse programming is required. Refer to Appendix A for an example discrete implementation.

Figure 3-2 shows the digital connections between SoC and PMIC for PDN#1. This image also shows the digital pins that require external pull-up resistors. The PMIC enable pin (EN/PB/VSENSE) can be driven with the power-good signal of the pre-regulator. Alternatively, this signal can be pulled up to PMIC_VSYS if the pre-regulator does not integrate a power-good signal. The PMIC nRSTOUT drives the RTC power-on reset (RTC_PORz) and SoC main reset (PORz). This is allowed when not supporting RTC only and RTC + IO + DDR low power modes. The PMIC_LPM_EN0 drives the PMIC MODE/STBY pin to switch the DCDC switching mode from forced-PWM to auto-PFM and to improve power efficiency during DeepSleep and Standby/OS Idle low power modes. This is optional and require the PMIC MODE/STBY pin to be configured as "MODE".

SoC - PMIC Digital Connections for PDN#1 Figure 3-2 SoC - PMIC Digital Connections for PDN#1
Note: PMIC_LPM_EN0 does not require an external pull-up resistor; The SoC has an internal pullup resistor that drives the signal high if VDDS_RTC is powered. PORz is 3.3V tolerant and the external pull-up resistor can be connected to a 1.8V supply or 3.3V supply as long as VDDS_OSC0 is powered.
PMIC BOM Example Figure 3-3 PMIC BOM Example