SLVAFW3B March   2025  – October 2025 AM62L , TPS65214

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Power Management IC (PMIC) Overview
  6. 3Low Power Modes and Power Supply Optimization
    1. 3.1 PDN#1: Optimized Power Design for BOM Size and Cost
    2. 3.2 PDN#2: Optimized Power Design for Lowest Suspend Power
    3. 3.3 PDN#3: Fully Flexible Power Design
    4. 3.4 PDN#4: Power Supply Implementation for DDR4
  7. 4Power-Up Sequence
  8. 5Power-Down Sequence
  9. 6Summary
  10. 7References
  11.   A Appendix A: Discrete Power Implementation for PDN#1
  12.   B Revision History

5 Power-Down Sequence

Figure 5-1 shows the power-down sequencing using the TPS6521401 OTP configuration as a reference. This power-down sequence do not cover the SoC sequencing from Active to Low Power Modes. The diagram only represents the power-down sequence when an OFF request is sent to the PMIC by hardware (pulling the enable pin low) or by software (I2C OFF request). Refer to the AM62L data sheet for a detailed sequencing waveforms and requirements.

AM62L Power-Down Sequence Figure 5-1 AM62L Power-Down Sequence